| 1 | /* |
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| 2 | Availink avl2108 - DVBS/S2 Satellite demod driver with Sharp BS2S7HZ6360 tuner |
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| 3 | |
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| 4 | Copyright (C) 2009 Duolabs Spa |
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| 5 | |
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| 6 | This program is free software; you can redistribute it and/or modify |
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| 7 | it under the terms of the GNU General Public License as published by |
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| 8 | the Free Software Foundation; either version 2 of the License, or |
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| 9 | (at your option) any later version. |
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| 10 | |
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| 11 | This program is distributed in the hope that it will be useful, |
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| 12 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
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| 13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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| 14 | GNU General Public License for more details. |
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| 15 | |
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| 16 | You should have received a copy of the GNU General Public License |
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| 17 | along with this program; if not, write to the Free Software |
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| 18 | Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. |
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| 19 | */ |
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| 20 | |
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| 21 | #ifndef _AVL2108_REG_H |
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| 22 | #define _AVL2108_REG_H |
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| 23 | |
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| 24 | /* Generic ops like reset and PLL */ |
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| 25 | #define REG_CORE_RESET_B 0x600000 |
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| 26 | #define REG_RESET 0x6C0000 |
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| 27 | #define PLL_R1 0x6C0080 |
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| 28 | #define PLL_R2 0x6C00C0 |
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| 29 | #define PLL_R3 0x6C0100 |
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| 30 | #define PLL_R4 0x6C0140 |
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| 31 | #define PLL_R5 0x6C0180 |
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| 32 | #define PLL_SOFTVALUE_EN 0x6C0200 |
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| 33 | |
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| 34 | #define REG_ROM_VER 0x00100000 /**< Chip version */ |
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| 35 | #define REG_PATCH_VER 0x000004A8 /**< Patch version */ |
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| 36 | #define REG_ERROR_MSG 0x0000042C |
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| 37 | #define REG_RX_CMD 0x00000400 |
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| 38 | #define REG_CORE_RDY_WORD 0x00000434 |
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| 39 | |
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| 40 | /* Generic ops */ |
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| 41 | #define DEMOD_OP_NOOP 0x00 |
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| 42 | #define DEMOD_OP_LD_DEFAULT 0x01 |
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| 43 | #define DEMOD_OP_INIT_GO 0x02 |
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| 44 | #define DEMOD_OP_RESET_BERPER 0x03 |
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| 45 | #define DEMOD_OP_HALT 0x04 |
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| 46 | #define DEMOD_OP_SLEEP 0x05 |
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| 47 | #define DEMOD_OP_WAKE 0x06 |
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| 48 | #define DEMOD_OP_ND_SCAN 0x08 |
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| 49 | #define DEMOD_OP_STDOUT_MODE 0x09 |
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| 50 | #define DEMOD_OP_TUNER_LOCK 0x0b |
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| 51 | #define DEMOD_OP_TUNER_LOCK_ST 0x0c |
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| 52 | #define DEMOD_OP_HELLO 0xFF |
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| 53 | |
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| 54 | #define CI_FLAG_IQ_BIT 0x00 |
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| 55 | #define CI_FLAG_IQ_BIT_MASK 0x01 |
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| 56 | #define CI_FLAG_IQ_NO_SWAPPED 0x00 |
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| 57 | |
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| 58 | #define CI_FLAG_DVBS2_BIT 0x02 |
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| 59 | #define CI_FLAG_DVBS2_BIT_MASK 0x1C |
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| 60 | #define CI_FLAG_DVBS2_UNDEF 0x04 |
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| 61 | |
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| 62 | #define CI_FLAG_IQ_AUTO_BIT 0x05 |
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| 63 | #define CI_FLAG_IQ_AUTO_BIT_MASK 0x20 |
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| 64 | #define CI_FLAG_IQ_AUTO_BIT_AUTO 0x01 |
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| 65 | |
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| 66 | #define CI_FLAG_LOCK_MODE_BIT 0x06 |
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| 67 | #define CI_FLAG_LOCK_MODE_BIT_MASK 0x40 |
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| 68 | |
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| 69 | #define TUNER_LOCKED 0x1 |
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| 70 | |
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| 71 | #define TUNER_LPF 340 /*< Tuner's LPF in 100KHz */ |
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| 72 | |
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| 73 | #define FUNC_MODE_DEMOD 0x0 |
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| 74 | #define FUNC_MODE_BLIND 0x1 |
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| 75 | |
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| 76 | #define LOCK_MODE_FIXED 0x0 |
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| 77 | #define LOCK_MODE_ADAPTIVE 0x1 |
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| 78 | |
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| 79 | /* RF AGC Polarisation */ |
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| 80 | #define AGC_POL_NORMAL 0x0 |
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| 81 | #define AGC_POL_INVERT 0x1 |
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| 82 | |
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| 83 | /* Tuner registers */ |
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| 84 | #define REG_TUNER_FREQ_100KHZ 0x000005D0 /**< Tuner frequency in 100KHz */ |
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| 85 | #define REG_TUNER_LPF_100KHZ 0x000005D2 /**< Tuner Low Pass Filter */ |
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| 86 | #define REG_TUNER_SLAVE_ADDR 0x000005D4 /**< Tuner slave address */ |
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| 87 | #define REG_TUNER_MAX_LPF_100KHZ 0x000005D6 /**< Tuner Low Pass Filter maximum */ |
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| 88 | #define REG_TUNER_LPF_MARGIN_100KHZ 0x000005D8 /**< Tuner Low Pass Filter margin */ |
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| 89 | #define REG_TUNER_USE_INTERNAL_CTRL 0x000005DA /**< Tuner control mode select */ |
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| 90 | |
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| 91 | #define TUNER_SLAVE_ADDR 0xC0 |
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| 92 | |
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| 93 | /* i2c repeater registers for tuner */ |
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| 94 | #define REG_I2C_SPEED_KHZ 0x000005CC |
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| 95 | #define REG_I2C_CMD 0x00000404 |
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| 96 | #define REG_I2C_RSP 0x00000418 |
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| 97 | #define REG_TUNER_STATUS 0x000007B2 |
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| 98 | |
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| 99 | #define TUNER_I2C_CLK 200 /**< Tuner's clock speed in KHz dedicated to the I2C bus */ |
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| 100 | |
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| 101 | #define I2C_CMD_LEN 0x14 |
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| 102 | #define I2C_RSP_LEN 0x14 |
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| 103 | #define I2C_NOOP 0x00 |
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| 104 | #define I2C_INIT 0x01 |
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| 105 | #define I2C_WRITE 0x02 |
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| 106 | #define I2C_READ 0x03 |
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| 107 | |
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| 108 | /* Blind-scan registers */ |
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| 109 | #define REG_BLIND_SCAN_RETRIES 0x000005F8 /**< Blind scan retries */ |
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| 110 | #define REG_BLIND_SCAN_SRATE_TO_HZ 0x00002472 |
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| 111 | #define REG_BLIND_SCAN_CARIER_FREQ_TO_KHZ 0x00002484 |
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| 112 | #define REG_BLIND_SCAN_CARRIER_DB 0x00002486 |
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| 113 | |
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| 114 | /* Receiver registers */ |
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| 115 | #define REG_RF_AGC_POL 0x0000043c |
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| 116 | #define REG_SPEC_INV 0x00000470 |
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| 117 | #define REG_MPEG_ERR_SIGNAL_POL 0x00000458 /**< MPEG error signal polarity */ |
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| 118 | #define REG_MPEG_SERIAL_OUT_SEL 0x00000460 /**< MPEG serial output pin select */ |
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| 119 | #define REG_MPEG_SERIAL_BIT_SEQ 0x00000468 /**< MPEG serial bit sequence */ |
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| 120 | #define REG_MPEG_POS_EDGE 0x000004DC /**< MPEG clock edge select */ |
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| 121 | #define REG_MPEG_SERIAL 0x000004DE /**< MPEG output mode */ |
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| 122 | #define REG_MPEG_MODE 0x0000045C /**< MPEG output mode select */ |
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| 123 | #define REG_MPEG_SERIAL_CLK_N 0x000004E0 /**< MPEG serial clock N */ |
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| 124 | #define REG_MPEG_SERIAL_CLK_D 0x000004E2 /**< MPEG serial clock D */ |
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| 125 | #define REG_MPEG_OUTPUT 0x006C0024 /**< MPEG output enable */ |
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| 126 | #define REG_ERR_MODE_CTRL 0x000004F8 /**< Error mode control */ |
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| 127 | #define REG_SNR_DB 0x00000680 |
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| 128 | #define REG_SNR_LINEAR 0x00000690 |
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| 129 | #define REG_DMD_CLK_MHZ 0x00000580 |
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| 130 | #define REG_FEC_CLK_MHZ 0x00000582 |
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| 131 | #define REG_MPEG_CLK_MHZ 0x00000584 |
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| 132 | #define REG_SRATE_HZ 0x00000490 |
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| 133 | #define REG_FORMAT 0x0000044C |
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| 134 | #define REG_ALPHA 0x00000440 |
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| 135 | #define REG_ALPHA_SETTING 0x0000046C |
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| 136 | #define REG_DECODE_MODE 0x0000248A |
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| 137 | #define REG_IQ_SWAP_MODE 0x00002488 |
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| 138 | #define REG_CARRIER_FREQ_HALF_RANGE_MHZ 0x0000058A |
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| 139 | #define REG_FEC_LOCK 0x00000790 |
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| 140 | #define REG_BER 0x000007F8 |
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| 141 | #define REG_AAGC_REF 0x000004CA |
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| 142 | #define REG_AAGC 0x0040004C |
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| 143 | #define REG_DVBS_BER_ADDR 0x00002480 |
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| 144 | #define REG_LOCK_MODE 0x00002478 |
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| 145 | #define REG_FUNCTIONAL_MODE 0x00002476 |
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| 146 | #define REG_MPEG_PERSISTENT_CLK_MODE 0x0000246E /**< MPEG persistent clk mode */ |
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| 147 | |
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| 148 | /* Diseqc registers */ |
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| 149 | #define REG_DISEQC_TX_CTRL 0x00700000 |
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| 150 | #define REG_DISEQC_TONE_FRAC_N 0x00700004 |
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| 151 | #define REG_DISEQC_TONE_FRAC_D 0x00700008 |
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| 152 | #define REG_DISEQC_TX_ST 0x0070000C |
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| 153 | #define REG_DISEQC_RX_MSG_TMR 0x00700014 |
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| 154 | #define REG_DISEQC_RX_CTRL 0x0070001C |
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| 155 | #define REG_DISEQC_SRST 0x00700020 |
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| 156 | #define REG_DISEQC_SAMP_FRAC_N 0x00700028 |
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| 157 | #define REG_DISEQC_SAMP_FRAC_D 0x0070002C |
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| 158 | #define REG_DISEQC_TX_FIFO_MAP 0x00700080 |
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| 159 | |
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| 160 | /* Diseqc data */ |
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| 161 | #define DISEQC_TONE_FREQ 22 /*< In KHz */ |
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| 162 | |
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| 163 | #define DISEQC_TX_GAP_15 0x0000 /*< 15ms gap: When transmitting, there is gap between TONE0 and TONE1 */ |
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| 164 | #define DISEQC_TX_GAP_20 0x0001 /*< 20ms gap */ |
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| 165 | #define DISEQC_TX_GAP_25 0x0002 /*< 25ms gap */ |
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| 166 | #define DISEQC_TX_GAP_30 0x0003 /*< 30ms gap */ |
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| 167 | |
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| 168 | #define DISEQC_TX_MODE_MOD 0x0000 /*< Modulation mode */ |
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| 169 | #define DISEQC_TX_MODE_TONE0 0x0010 /*< Send tone 0 */ |
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| 170 | #define DISEQC_TX_MODE_TONE1 0x0020 /*< Send tone 1 */ |
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| 171 | #define DISEQC_TX_MODE_CONT 0x0030 /*< Continuous send pulses */ |
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| 172 | |
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| 173 | #define DISEQC_WAVEFORM_NORMAL 0x0000 /*< Normal wave mode */ |
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| 174 | #define DISEQC_WAVEFORM_ENVELOPE 0x0100 /*< Wave is sent using envelopes */ |
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| 175 | |
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| 176 | #define DISEQC_RX_150 0x0000 /*< Wait 150 ms before closing the input FIFO */ |
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| 177 | #define DISEQC_RX_170 0x1000 /*< Wait 170 ms */ |
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| 178 | #define DISEQC_RX_190 0x2000 /*< Wait 190 ms */ |
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| 179 | #define DISEQC_RX_210 0x3000 /*< Wait 210 ms */ |
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| 180 | |
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| 181 | /* Diseqc status */ |
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| 182 | #define DISEQC_STATUS_UNINIT 0x00 |
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| 183 | #define DISEQC_STATUS_INIT 0x01 |
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| 184 | #define DISEQC_STATUS_CONTINUOUS 0x02 |
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| 185 | #define DISEQC_STATUS_TONE 0x03 |
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| 186 | #define DISEQC_STATUS_MOD 0x04 |
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| 187 | |
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| 188 | /* MPEG data */ |
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| 189 | #define MPEG_FORMAT_TS 0x0 /*< Transport stream */ |
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| 190 | #define MPEG_FORMAT_TS_PAR 0x1 /*< Transport stream + Parity */ |
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| 191 | |
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| 192 | #define MPEG_MODE_PARALLEL 0x0 /*< Output parallel data */ |
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| 193 | #define MPEG_MODE_SERIAL 0x1 /*< Output serial data */ |
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| 194 | |
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| 195 | #define MPEG_CLK_MODE_FALLING 0x0 /*< MPEG data sampled on clock's falling edge */ |
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| 196 | #define MPEG_CLK_MODE_RISING 0x1 /*< MPEG data sampled on clock's rising edge */ |
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| 197 | |
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| 198 | #endif /* _AVL2108_REG_H */ |
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