source: tools/oebuild/data/pti_np/pti.h

Last change on this file was 45168, checked in by obi, 3 years ago

add oebuild building files
  • Property svn:executable set to *
File size: 26.6 KB
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1#ifndef _PTI_H_
2#define _PTI_H_
3
4#include <linux/init.h>
5#include <linux/slab.h>
6#include <linux/wait.h>
7#include <linux/module.h>
8#include <linux/usb.h>
9#include <linux/delay.h>
10#include <linux/time.h>
11#include <linux/errno.h>
12
13#include <linux/version.h>
14
15#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,32)
16#include <linux/semaphore.h>
17#else
18#include <asm/semaphore.h>
19#endif
20#include <linux/platform_device.h>
21#include <linux/mutex.h>
22
23#include <asm/io.h>
24
25#if defined (CONFIG_KERNELVERSION) || LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,32)
26#include <linux/bpa2.h>
27#else
28#include <linux/bigphysarea.h>
29#endif
30/* doesn't run very stable on ufs910,
31 * all other should try this
32 */
33#undef use_irq
34
35//#define A18
36//#define REL23
37
38//#define PLAYER211
39
40#if defined (CONFIG_CPU_SUBTYPE_STX7111)
41
42#define REL29
43#define SECURE_LITE2
44
45#elif defined (CONFIG_CPU_SUBTYPE_STX7105)
46
47#define REL29
48#define SECURE_LITE2
49
50#else
51
52#define A18
53/* fixme:
54 * ! all 7109er architectures should use secure lite 1 but
55 * this is not implemented currently.
56 */
57#endif
58
59/* external declaration */
60struct tBuffer;
61
62#define TC_DMA_THRESHOLD_LOW 1
63#define TC_DMA_THRESHOLD_HIGH 128
64
65#define PTI_DMAEMPTY_EN (0x0038)
66
67#if !defined(SECURE_LITE2)
68#define TC_DATA_RAM_SIZE 6656 /* (6.5 * 1024) */
69#define TC_CODE_RAM_SIZE 7680 /* (7.5 * 1024) */
70#else
71#define TC_DATA_RAM_SIZE 13824 /* (13.5 * 1024) */
72#define TC_CODE_RAM_SIZE 16384 /* (16 * 1024) */
73#endif
74
75#define TC_NUMBER_OF_HARDWARE_SECTION_FILTERS 32
76
77#if defined(SECURE_LITE2)
78#define TC_NUMBER_OF_HARDWARE_NOT_FILTERS 128
79#else
80#define TC_NUMBER_OF_HARDWARE_NOT_FILTERS 32
81#endif
82
83#if defined(SECURE_LITE2)
84#define SF_BYTES_PER_CAM 1024 /* Fixed value from hardware specs. */
85#else
86#define SF_BYTES_PER_CAM 768 /* Fixed value from hardware specs. */
87#endif
88
89#define SF_FILTER_LENGTH 8 /* Minimum CAM filter length, must be multiple of 8 (8=short section filter mode) */
90#define SF_CAMLINE_WIDTH 4 /* Fixed value from hardware specs. */
91#define SF_BYTES_PER_MIN_ALLOC ( SF_CAMLINE_WIDTH * (SF_FILTER_LENGTH * 2)) /* N filters of M bytes & masks */
92
93#define SF_NUM_BLOCKS_PER_CAM ( SF_BYTES_PER_CAM / SF_BYTES_PER_MIN_ALLOC )
94#define SF_NUM_FILTERS_PER_BLOCK ( SF_CAMLINE_WIDTH * 2 ) /* block spans the 2 CAMs each holding SF_CAMLINE_WIDTH filters */
95
96/* MAGIC numbers for the CAM_CFG register */
97#define CAM_CFG_8_FILTERS 0x0000 /* bits 5:3 (number of filters) */
98#define CAM_CFG_16_FILTERS 0x0008
99#define CAM_CFG_32_FILTERS 0x0010
100#define CAM_CFG_64_FILTERS 0x0018
101#define CAM_CFG_96_FILTERS 0x0020
102
103#define INVALID_FILTER_INDEX ((u32)0xffffffff)
104
105#define TC_INVALID_PID ((unsigned int)0xe000)
106#define TC_INVALID_LINK ((unsigned int)0xf000)
107#define SESSION_NOT_ALLOCATED 0xDEAD
108
109#define STATUS_FLAGS_TRANSPORT_ERROR 0x00000001
110#define STATUS_FLAGS_SECTION_CRC_ERROR 0x00000002
111#define STATUS_FLAGS_INVALID_DESCRAMBLE_KEY 0x00000004
112#define STATUS_FLAGS_INVALID_PARAMETER 0x00000008
113#define STATUS_FLAGS_INVALID_CC 0x00000010
114#define STATUS_FLAGS_TC_CODE_FAULT 0x00000020
115#define STATUS_FLAGS_PACKET_SIGNAL 0x00000040
116#define STATUS_FLAGS_PES_ERROR 0x00000080
117
118#define STATUS_FLAGS_DMA_COMPLETE 0x00000100
119#define STATUS_FLAGS_SUBSTITUTE_COMPLETE 0x00000400
120#define STATUS_FLAGS_RECORD_BUFFER_OVERFLOW 0x00000800
121#define STATUS_FLAGS_CWP_FLAG 0x00002000 /* (DSS only) */
122#define STATUS_FLAGS_INVALID_LINK 0x00004000
123#define STATUS_FLAGS_BUFFER_OVERFLOW 0x00008000
124
125#define STATUS_FLAGS_ADAPTATION_EXTENSION_FLAG 0x00010000 /* (DVB only) */
126#define STATUS_FLAGS_PRIVATE_DATA_FLAG 0x00020000 /* (DVB only) */
127#define STATUS_FLAGS_SPLICING_POINT_FLAG 0x00040000 /* (DVB only) */
128#define STATUS_FLAGS_OPCR_FLAG 0x00080000 /* (DVB only) */
129#define STATUS_FLAGS_PCR_FLAG 0x00100000
130#define STATUS_FLAGS_PRIORITY_INDICATOR 0x00200000 /* (DVB only) */
131#define STATUS_FLAGS_RANDOM_ACCESS_INDICATOR 0x00400000 /* (DVB only) */
132#define STATUS_FLAGS_CURRENT_FIELD_FLAG 0x00400000 /* (DSS only) */
133#define STATUS_FLAGS_DISCONTINUITY_INDICATOR 0x00800000 /* (DVB only) */
134#define STATUS_FLAGS_MODIFIABLE_FLAG 0x00800000 /* (DSS only) */
135
136#define STATUS_FLAGS_START_CODE_FLAG 0x01000000 /* (DVB only) */
137#define STATUS_FLAGS_TIME_CODE 0x01000000 /* (DSS only) */
138#define STATUS_FLAGS_PUSI_FLAG 0x02000000 /* (DVB only) */
139#define STATUS_FLAGS_SCRAMBLE_CHANGE 0x04000000
140#define STATUS_FLAGS_FIRST_RECORDED_PACKET 0x08000000
141#define STATUS_FLAGS_BUNDLE_BOUNDARY 0x10000000 /* (DSS only) */
142#define STATUS_FLAGS_AUXILIARY_PACKET 0x20000000 /* (DSS only) */
143#define STATUS_FLAGS_SESSION_NUMBER_MASK 0x30000000 /* (DVB only) */
144#define STATUS_FLAGS_PACKET_SIGNAL_RECORD_BUFFER 0x40000000
145#define STATUS_FLAGS_INDX_TIMEOUT_TICK 0x80000000 /* Only used for STPTI_TIMER_TICK feature */
146
147#define TC_GLOBAL_DATA_DISCARD_SYNC_BYTE_SET 0x0001
148
149/* SessionSectionParams: */
150
151#define TC_SESSION_INFO_FILTER_TYPE_FIELD 0xF000
152
153#define TC_SESSION_INFO_FILTER_TYPE_IREDETO_ECM 0x2000
154#define TC_SESSION_INFO_FILTER_TYPE_IREDETO_EMM 0x3000
155#define TC_SESSION_INFO_FILTER_TYPE_SHORT 0x4000
156#define TC_SESSION_INFO_FILTER_TYPE_LONG 0x5000
157#define TC_SESSION_INFO_FILTER_TYPE_MAC 0x6000
158#define TC_SESSION_INFO_FILTER_TYPE_NEG_MATCH 0x7000
159
160#define TC_SESSION_INFO_FORCECRCSTATE 0x0001
161#define TC_SESSION_INFO_DISCARDONCRCERROR 0x0002
162
163#define TC_SESSION_DVB_PACKET_FORMAT 0x0010
164
165#define TC_DMA_CONFIG_SIGNAL_MODE_FLAGS_SIGNAL_DISABLE 0x1
166#define TC_DMA_CONFIG_SIGNAL_MODE_TYPE_MASK 0xe
167#define TC_DMA_CONFIG_SIGNAL_MODE_TYPE_NO_SIGNAL 0x0
168#define TC_DMA_CONFIG_SIGNAL_MODE_TYPE_QUANTISATION 0x2
169#define TC_DMA_CONFIG_SIGNAL_MODE_TYPE_EVERY_TS 0x4
170#define TC_DMA_CONFIG_SIGNAL_MODE_SWCDFIFO 0x8
171#define TC_DMA_CONFIG_OUTPUT_WITHOUT_META_DATA 0x10
172#define TC_DMA_CONFIG_WINDBACK_ON_ERROR 0x20
173
174#define SESSION_USE_MERGER_FOR_STC 0x8000
175#define SESSION_MASK_STC_SOURCE 0x7FFF
176
177#define SLOT_STATE_INITIAL_SCRAMBLE_STATE 0x4000
178
179#define STPTI_BUFFER_ALIGN_MULTIPLE 0x20
180#define STPTI_BUFFER_SIZE_MULTIPLE 0x20
181
182#define DMAScratchAreaSize (STPTI_BUFFER_SIZE_MULTIPLE+STPTI_BUFFER_ALIGN_MULTIPLE)
183#define NO_OF_DVB_STATUS_BLOCKS 200
184
185#define NO_OF_STATUS_BLOCKS NO_OF_DVB_STATUS_BLOCKS
186
187#define TC_DSRAM_BASE 0x8000
188
189#define TC_SLOT_TYPE_NULL 0x0000
190#define TC_SLOT_TYPE_SECTION 0x0001
191#define TC_SLOT_TYPE_PES 0x0002
192#define TC_SLOT_TYPE_RAW 0x0003
193#define TC_SLOT_TYPE_EMM 0x0005
194#define TC_SLOT_TYPE_ECM 0x0006
195
196#define TC_MAIN_INFO_PES_STREAM_ID_FILTER_ENABLED 0x0100
197
198#define TC_MAIN_INFO_SLOT_STATE_ODD_SCRAMBLED 0x0001
199#define TC_MAIN_INFO_SLOT_STATE_TRANSPORT_SCRAMBLED 0x0002
200#define TC_MAIN_INFO_SLOT_STATE_SCRAMBLED 0x0004
201#define TC_MAIN_INFO_SLOT_STATE_SCRAMBLE_STATE_FIELD (TC_MAIN_INFO_SLOT_STATE_SCRAMBLED | \
202                                                      TC_MAIN_INFO_SLOT_STATE_TRANSPORT_SCRAMBLED| \
203                                                      TC_MAIN_INFO_SLOT_STATE_ODD_SCRAMBLED)
204
205#define TC_MAIN_INFO_SLOT_STATE_DMA_IN_PROGRESS 0x1000
206#define TC_MAIN_INFO_SLOT_STATE_SEEN_PACKET 0x2000
207#define TC_MAIN_INFO_SLOT_STATE_SEEN_TS_SCRAMBLED 0x4000
208#define TC_MAIN_INFO_SLOT_STATE_SEEN_PES_SCRAMBLED 0x8000
209#define TC_MAIN_INFO_SLOT_STATE_SEEN_FIELD (TC_MAIN_INFO_SLOT_STATE_SEEN_PACKET | \
210                                            TC_MAIN_INFO_SLOT_STATE_SEEN_TS_SCRAMBLED | \
211                                            TC_MAIN_INFO_SLOT_STATE_SEEN_PES_SCRAMBLED)
212
213#define TC_MAIN_INFO_SLOT_MODE_ALTERNATE_OUTPUT_CLEAR 0x0010
214#define TC_MAIN_INFO_SLOT_MODE_ALTERNATE_OUTPUT_DESCRAMBLED 0x0020
215#define TC_MAIN_INFO_SLOT_MODE_ALTERNATE_OUTPUT_FIELD (TC_MAIN_INFO_SLOT_MODE_ALTERNATE_OUTPUT_CLEAR | \
216                                                       TC_MAIN_INFO_SLOT_MODE_ALTERNATE_OUTPUT_DESCRAMBLED)
217
218#define TC_MAIN_INFO_SLOT_MODE_IGNORE_SCRAMBLING 0x0040
219#define TC_MAIN_INFO_SLOT_MODE_INJECT_SEQ_ERROR_MODE 0x0080
220#define TC_MAIN_INFO_SLOT_MODE_SUBSTITUTE_STREAM 0x0100
221
222#define TC_MAIN_INFO_SLOT_MODE_DMA_1 0x0200
223#define TC_MAIN_INFO_SLOT_MODE_DMA_2 0x0400
224#define TC_MAIN_INFO_SLOT_MODE_DMA_3 0x0600
225#define TC_MAIN_INFO_SLOT_MODE_DMA_FIELD 0x0600
226
227#define TC_MAIN_INFO_SLOT_MODE_DISABLE_CC_CHECK 0x0800
228
229/* For Watch & record reuses Startcode detection word*/
230#define TC_MAIN_INFO_REC_BUFFER_MODE_ENABLE 0x0100
231#define TC_MAIN_INFO_REC_BUFFER_MODE_DESCRAMBLE 0x0200
232
233#define TC_MAIN_INFO_STARTCODE_DETECTION_OFFSET_MASK 0x00FF
234
235#define IIF_SYNC_CONFIG_USE_SOP 0x01
236
237typedef enum STPTI_StreamID_s
238{
239        STPTI_STREAM_ID_TSIN0 = 0x20,
240        STPTI_STREAM_ID_TSIN1,
241        STPTI_STREAM_ID_TSIN2,
242#if defined(CONFIG_CPU_SUBTYPE_STX7105) || defined(CONFIG_CPU_SUBTYPE_STX7111)
243        STPTI_STREAM_ID_TSIN3,
244#endif
245        STPTI_STREAM_ID_SWTS0,
246#if defined(ST_7101) || defined(CONFIG_CPU_SUBTYPE_STX7105) || defined(CONFIG_CPU_SUBTYPE_STB7100) || defined(CPU_SUBTYPE_STX7100) || defined(CONFIG_CPU_SUBTYPE_STX7111)
247        STPTI_STREAM_ID_SWTS1,
248        STPTI_STREAM_ID_SWTS2,
249#endif
250        STPTI_STREAM_ID_ALTOUT,
251        STPTI_STREAM_ID_NOTAGS = 0x80, /* if tsmerger not configured to emit tag bytes */
252        STPTI_STREAM_ID_NONE /*Use to deactivate a virtual PTI*/
253
254} STPTI_StreamID_t ;
255
256/* BOOL type constant values */
257#ifndef TRUE
258#define TRUE (1 == 1)
259#endif
260#ifndef FALSE
261#define FALSE (!TRUE)
262#endif
263
264typedef volatile u32 *STPTI_DevicePtr_t;
265
266#if defined(A18) || defined(REL23) || defined(REL29)
267
268typedef volatile struct TCSessionInfo_s
269{
270        u16 SessionInputPacketCount;
271        u16 SessionInputErrorCount;
272
273        u16 SessionCAMFilterStartAddr; /* PTI4L (ram cam) only */
274        u16 SessionCAMConfig; /* PTI4L (ram cam) only */
275
276        u16 SessionPIDFilterStartAddr;
277        u16 SessionPIDFilterLength;
278
279        u16 SessionSectionParams; /* SF_Config (crc & filter type etc.) */
280        u16 SessionTSmergerTag;
281
282        u16 SessionProcessState;
283        u16 SessionModeFlags;
284
285        u16 SessionNegativePidSlotIdent;
286        u16 SessionNegativePidMatchingEnable;
287
288        u16 SessionUnmatchedSlotMode;
289        u16 SessionUnmatchedDMACntrl_p;
290
291        u16 SessionInterruptMask0;
292        u16 SessionInterruptMask1;
293
294        u16 SessionSTCWord0;
295        u16 SessionSTCWord1;
296
297        u16 SessionSTCWord2;
298        u16 SessionDiscardParams;
299
300        u32 SessionPIPFilterBytes;
301        u32 SessionPIPFilterMask;
302
303        u32 SessionCAPFilterBytes;
304        u32 SessionCAPFilterMask;
305
306        u16 SessionEMMFilterOffset;
307        u16 SessionSpare;
308
309        u32 SectionEnables_0_31;
310
311        u32 SectionEnables_32_63;
312
313#if defined(SECURE_LITE2)
314        u32 SectionEnables_64_95;
315
316        u32 SectionEnables_96_127;
317
318        u16 SessionLastEvtTick_0;
319        u16 SessionLastEvtTick_1;
320
321        u16 SessionTickDMA_p;
322        u16 SessionTickDMA_Slot;
323
324        u16 SessionSBoxInfo;
325        u16 SessionSpareRegister;
326#endif
327
328} TCSessionInfo_t;
329
330#else
331
332typedef volatile struct TCSessionInfo_s
333{
334        u16 SessionInputPacketCount;
335        u16 SessionInputErrorCount;
336
337        u16 SessionCAMFilterStartAddr; /* PTI4L (ram cam) only */
338        u16 SessionCAMConfig; /* PTI4L (ram cam) only */
339
340        u16 SessionPIDFilterStartAddr;
341        u16 SessionPIDFilterLength;
342
343        u16 SessionSectionParams; /* SF_Config (crc & filter type etc.) */
344        u16 SessionTSmergerTag;
345
346        u16 SessionProcessState;
347        u16 SessionModeFlags;
348
349        u16 SessionNegativePidSlotIdent;
350        u16 SessionNegativePidMatchingEnable;
351
352        u16 SessionUnmatchedSlotMode;
353        u16 SessionUnmatchedDMACntrl_p;
354
355        u16 SessionInterruptMask0;
356        u16 SessionInterruptMask1;
357
358        u32 SectionEnables_0_31;
359        u32 SectionEnables_32_63;
360
361        u16 SessionSTCWord0;
362        u16 SessionSTCWord1;
363
364        u16 SessionSTCWord2;
365        u16 SessionDiscardParams;
366
367        u32 SessionPIPFilterBytes;
368        u32 SessionPIPFilterMask;
369
370        u32 SessionCAPFilterBytes;
371        u32 SessionCAPFilterMask;
372
373} TCSessionInfo_t;
374#endif
375
376#if defined(A18) || defined(REL23) || defined(REL29)
377typedef volatile struct TCGlobalInfo_s
378{
379        u16 GlobalPacketHeader; /* (TC) */
380        u16 GlobalHeaderDesignator; /* (TC) */
381
382        u32 GlobalLastQWrite; /* (TC) GlobalLastQWrite_0:16 GlobalLastQWrite_1:16 */
383
384        u16 GlobalQPointsInPacket; /* (TC) */
385        u16 GlobalProcessFlags; /* (TC) */
386
387        u16 GlobalSlotMode; /* (TC) */
388        u16 GlobalDMACntrl_p; /* (TC) */
389
390        u32 GlobalPktCount; /* (TC) Global Input Packet Count */
391
392        u16 GlobalSignalModeFlags; /* (TC) */
393        u16 GlobalCAMArbiterIdle; /* (TC) For GNBvd18811 */
394
395        u16 GlobalSFTimeouts; /* (TC) */
396        u16 GlobalDTVPktBufferPayload_p; /* (TC) */
397
398        u16 GlobalResidue; /* (TC) */
399        u16 GlobalPid; /* (TC) */
400
401        u16 GlobalIIFCtrl; /* (TC) */
402        u16 GlobalProfilerCount; /* (TC) */
403
404        u16 GlobalRecordDMACntrl_p; /* (TC) Holds the address of the DMA structure for the Record Buffer */
405        u16 GlobalDescramblingAllowed; /* (TC) */
406
407        u16 GlobalCAMArbiterInhibit; /* (Host) For GNBvd18811 */
408        u16 GlobalModeFlags; /* (Host) */
409
410        u32 GlobalScratch; /* (Host) GlobalScratch_0 GlobalScratch_1 */
411
412        u16 GlobalNegativePidSlotIdent; /* (Host) */
413        u16 GlobalNegativePidMatchingEnable; /* (Host) */
414
415        u16 GlobalSwts_Params; /* (Host) */
416        u16 GlobalSFTimeout; /* (Host) */
417
418        u16 GlobalTSDumpDMA_p; /* (Host) */
419        u16 GlobalTSDumpCount; /* (Host) */
420
421        u16 GlobalICAMVersion; /* (Host) Host sets this word to tell TC what is the ICAM version used on this silicon */
422        u16 GlobalCAAllowEcmEmm; /* (TC) */
423
424        u16 GlobalCurrentSessionNo; /* (TC) Holds the current packet's session number, currently uses 8bits, when reused add mask to all the users appropriately */
425        u16 GlobalSpare1; /* FREE VARIABLE, USED FOR ALIGNMENT NOW */
426
427#ifndef REL29
428        /* Required for passage/overlay support */
429        u16 GlobalShadowMainInfo; /* (TC) */
430        u16 GlobalLegacyMainInfo; /* (TC) */
431#endif
432
433#if defined(SECURE_LITE2) && defined(A18)
434        u16 GlobalLastTickSessionNumber; /* (TC ) */
435        u16 GlobalTickEnable; /* (Host) */
436
437        u16 GlobalTickTemp_0; /* (TC) */
438        u16 GlobalTickTemp_1; /* (TC) */
439
440        u16 GlobalLastTickSlotNumber; /* (TC ) */
441        u16 GlobalSkipSetDiscard; /* (TC ) */
442#endif
443
444#if defined(SECURE_LITE2) && (defined(REL23) || defined(REL29))
445        u16 GlobalLastTickSessionNumber; /* (TC ) */
446        u16 GlobalTickEnable; /* (Host) */
447
448        u16 GlobalTickTemp_0; /* (TC) */
449        u16 GlobalTickTemp_1; /* (TC) */
450
451        u16 GlobalLastTickSlotNumber; /* (TC ) */
452        u16 GlobalFRPFirstStatBlkFlag; /* (TC ) */
453
454        u16 GlobalLast16ByteBlockStart; /* (TC ) */
455        u16 GlobalResidueStart; /* (TC ) */
456#endif
457
458} TCGlobalInfo_t;
459
460#else
461typedef volatile struct TCGlobalInfo_s
462{
463        u16 GlobalPacketHeader; /* (TC) */
464        u16 GlobalHeaderDesignator; /* (TC) */
465
466        u32 GlobalLastQWrite; /* (TC) GlobalLastQWrite_0:16 GlobalLastQWrite_1:16 */
467
468        u16 GlobalQPointsInPacket; /* (TC) */
469        u16 GlobalProcessFlags; /* (TC) */
470
471        u16 GlobalSlotMode; /* (TC) */
472        u16 GlobalDMACntrl_p; /* (TC) */
473
474        u32 GlobalPktCount; /* (TC) Global Input Packet Count */
475
476        u16 GlobalSignalModeFlags; /* (TC) */
477        u16 GlobalCAMArbiterIdle; /* (TC) For GNBvd18811 */
478
479        u16 GlobalSFTimeouts; /* (TC) */
480        u16 GlobalDTVPktBufferPayload_p; /* (TC) */
481
482        u16 GlobalResidue; /* (TC) */
483        u16 GlobalPid; /* (TC) */
484
485        u16 GlobalIIFCtrl; /* (TC) */
486        u16 GlobalProfilerCount; /* (TC) */
487
488        u16 GlobalRecordDMACntrl_p; /* (TC) Holds the address of the DMA structure for the Record Buffer */
489        u16 GlobalSpare1; /* (TC) Filter Address for the Start Code Detector */
490
491        u16 GlobalCAMArbiterInhibit; /* (Host) For GNBvd18811 */
492        u16 GlobalModeFlags; /* (Host) */
493
494        u32 GlobalScratch; /* (Host) GlobalScratch_0 GlobalScratch_1 */
495
496        u16 GlobalNegativePidSlotIdent; /* (Host) */
497        u16 GlobalNegativePidMatchingEnable; /* (Host) */
498
499        u16 GlobalSwts_Params; /* (Host) */
500        u16 GlobalSFTimeout; /* (Host) */
501
502        /* Only used for STPTI_TIMER_TICK feature */
503        u16 GlobalTSDumpDMA_p; /* (Host) */
504        u16 GlobalTSDumpCount; /* (Host) */
505
506        u16 GlobalLastTickSessionNumber; /* (TC ) */
507        u16 GlobalTickEnable; /* (Host) */
508
509        u16 GlobalTickTemp_0; /* (TC) */
510        u16 GlobalTickTemp_1; /* (TC) */
511
512        u16 GlobalLastTickSlotNumber; /* (TC ) */
513        u16 GlobalSkipSetDiscard; /* (TC ) */
514        /* End of STPTI_TIMER_TICK feature variables */
515
516} TCGlobalInfo_t;
517#endif
518
519typedef volatile struct
520{
521        u32 SFFilterDataLS;
522        u32 SFFilterMaskLS;
523        u32 SFFilterDataMS;
524        u32 SFFilterMaskMS;
525} TCSectionFilter_t;
526
527typedef volatile union TCFilterLine_s
528{
529        struct
530        {
531                u8 Filter[SF_CAMLINE_WIDTH];
532        } Element;
533
534        u32 Word;
535
536} TCFilterLine_t;
537
538typedef volatile struct TCCamEntry_s
539{
540        TCFilterLine_t Data;
541        TCFilterLine_t Mask;
542} TCCamEntry_t;
543
544typedef volatile struct TCCamIndex_s
545{
546        TCCamEntry_t Index[ SF_FILTER_LENGTH ];
547} TCCamIndex_t;
548
549typedef volatile struct TCSectionFilterArrays_s
550{
551        TCCamIndex_t CamA_Block[ SF_NUM_BLOCKS_PER_CAM ];
552#ifndef SECURE_LITE2
553        u32 ReservedA[256 / 4];
554#endif
555        TCCamIndex_t CamB_Block[ SF_NUM_BLOCKS_PER_CAM ];
556#ifndef SECURE_LITE2
557        u32 ReservedB[256 / 4];
558#endif
559        u32 NotFilter[ TC_NUMBER_OF_HARDWARE_NOT_FILTERS ];
560} TCSectionFilterArrays_t;
561
562typedef volatile struct TCDevice_s
563{
564        u32 PTIIntStatus0;
565        u32 PTIIntStatus1;
566        u32 PTIIntStatus2;
567        u32 PTIIntStatus3;
568
569        u32 PTIIntEnable0;
570        u32 PTIIntEnable1;
571        u32 PTIIntEnable2;
572        u32 PTIIntEnable3;
573
574        u32 PTIIntAck0;
575        u32 PTIIntAck1;
576        u32 PTIIntAck2;
577        u32 PTIIntAck3;
578
579        u32 TCMode;
580
581        u32 DMAempty_STAT; /* 3 bits RO */
582        u32 DMAempty_EN; /* 3 bits RW */
583
584        u32 TCPadding_0;
585
586        u32 PTIAudPTS_31_0;
587        u32 PTIAudPTS_32;
588
589        u32 PTIVidPTS_31_0;
590        u32 PTIVidPTS_32;
591
592        u32 STCTimer0;
593        u32 STCTimer1;
594
595        u32 TCPadding_1[(0x1000 - 22 * sizeof(u32)) / sizeof(u32)];
596
597        u32 DMA0Base;
598        u32 DMA0Top;
599        u32 DMA0Write;
600        u32 DMA0Read;
601        u32 DMA0Setup;
602        u32 DMA0Holdoff;
603        u32 DMA0Status;
604        u32 DMAEnable;
605
606        u32 DMA1Base;
607        u32 DMA1Top;
608        u32 DMA1Write;
609        u32 DMA1Read;
610        u32 DMA1Setup;
611        u32 DMA1Holdoff;
612        u32 DMA1CDAddr;
613        u32 DMASecStart;
614
615        u32 DMA2Base;
616        u32 DMA2Top;
617        u32 DMA2Write;
618        u32 DMA2Read;
619        u32 DMA2Setup;
620        u32 DMA2Holdoff;
621        u32 DMA2CDAddr;
622        u32 DMAFlush;
623
624        u32 DMA3Base;
625        u32 DMA3Top;
626        u32 DMA3Write;
627        u32 DMA3Read;
628        u32 DMA3Setup;
629        u32 DMA3Holdoff;
630        u32 DMA3CDAddr;
631        u32 DMAPTI3Prog;
632
633        u32 TCPadding_2[(0x2000 - (0x1000 + 32 * sizeof(u32))) / sizeof(u32)];
634
635        u32 TCPadding_4[(0x20e0 - 0x2000) / sizeof(u32)];
636
637        u32 IIFCAMode;
638
639        u32 TCPadding_5[(0x4000 - (0x2000 + 57 * sizeof(u32))) / sizeof(u32)];
640
641        TCSectionFilterArrays_t TC_SectionFilterArrays; /* std or ram cam */
642
643        u32 TCPadding_6[(0x6000 - (0x4000 + sizeof(TCSectionFilterArrays_t))) / sizeof(u32)];
644
645        u32 IIFFIFOCount;
646        u32 IIFAltFIFOCount;
647        u32 IIFFIFOEnable;
648        u32 TCPadding_3[1];
649        u32 IIFAltLatency;
650        u32 IIFSyncLock;
651        u32 IIFSyncDrop;
652        u32 IIFSyncConfig;
653        u32 IIFSyncPeriod;
654
655        u32 TCPadding_7[(0x7000 - (0x6000 + 9 * sizeof(u32))) / sizeof(u32)];
656
657        u32 TCRegA;
658        u32 TCRegB;
659        u32 TCRegC;
660        u32 TCRegD;
661        u32 TCRegP;
662        u32 TCRegQ;
663        u32 TCRegI;
664        u32 TCRegO;
665        u32 TCIPtr;
666        u32 TCRegE0;
667        u32 TCRegE1;
668        u32 TCRegE2;
669        u32 TCRegE3;
670        u32 TCRegE4;
671        u32 TCRegE5;
672        u32 TCRegE6;
673        u32 TCRegE7;
674
675        u32 TCPadding_8[(0x8000 - (0x7000 + 17 * sizeof(u32))) / sizeof(u32)];
676
677        u32 TC_Data[TC_DATA_RAM_SIZE / sizeof(u32)];
678
679        u32 TCPadding_9[(0xC000 - (0x8000 + TC_DATA_RAM_SIZE)) / sizeof(u32)];
680
681        u32 TC_Code[TC_CODE_RAM_SIZE / sizeof(u32)];
682} TCDevice_t;
683
684typedef struct
685{
686        STPTI_DevicePtr_t TC_CodeStart;
687        size_t TC_CodeSize;
688        STPTI_DevicePtr_t TC_DataStart;
689
690        STPTI_DevicePtr_t TC_LookupTableStart;
691        STPTI_DevicePtr_t TC_GlobalDataStart;
692        STPTI_DevicePtr_t TC_StatusBlockStart;
693        STPTI_DevicePtr_t TC_MainInfoStart;
694        STPTI_DevicePtr_t TC_DMAConfigStart;
695        STPTI_DevicePtr_t TC_DescramblerKeysStart;
696        STPTI_DevicePtr_t TC_TransportFilterStart;
697        STPTI_DevicePtr_t TC_SCDFilterTableStart;
698        STPTI_DevicePtr_t TC_PESFilterStart;
699        STPTI_DevicePtr_t TC_SubstituteDataStart;
700        STPTI_DevicePtr_t TC_SystemKeyStart; /* Descambler support */
701        STPTI_DevicePtr_t TC_SFStatusStart;
702        STPTI_DevicePtr_t TC_InterruptDMAConfigStart;
703        STPTI_DevicePtr_t TC_EMMStart;
704        STPTI_DevicePtr_t TC_ECMStart; /* Possibly redundant */
705        STPTI_DevicePtr_t TC_MatchActionTable;
706        STPTI_DevicePtr_t TC_SessionDataStart;
707        STPTI_DevicePtr_t TC_VersionID;
708
709        u16 TC_NumberCarousels;
710        u16 TC_NumberSystemKeys; /* Descambler support */
711        u16 TC_NumberDMAs;
712        u16 TC_NumberDescramblerKeys;
713        u16 TC_SizeOfDescramblerKeys;
714        u16 TC_NumberIndexs;
715        u16 TC_NumberPesFilters;
716        u16 TC_NumberSectionFilters;
717        u16 TC_NumberSlots;
718        u16 TC_NumberTransportFilters;
719        u16 TC_NumberEMMFilters;
720        u16 TC_SizeOfEMMFilter;
721        u16 TC_NumberECMFilters;
722        u16 TC_NumberOfSessions;
723        u16 TC_NumberSCDFilters;
724
725        int TC_AutomaticSectionFiltering;
726        int TC_MatchActionSupport;
727        int TC_SignalEveryTransportPacket;
728
729} STPTI_TCParameters_t;
730
731#define TC_SECONDARY_SLOT_NONE 0x0000
732
733typedef volatile struct TCMainInfo_s
734{
735        u16 SlotState;
736        u16 PacketCount;
737
738        u16 SlotMode;
739        u16 DescramblerKeys_p; /* a.k.a. CAPAccumulatedCount, CAPAccumulatedCount */
740
741        u16 DMACtrl_indices;
742        u16 IndexMask;
743
744        u16 SectionPesFilter_p;
745        u16 RemainingPESLength; /* a.k.a. ECMFilterMask */
746
747        u16 PESStuff; /* a.k.a. CAPFilterResult, RawCorruptionParams, ECMFilterData */
748        u16 StartCodeIndexing_p; /* a.k.a. RecordBufferMode */
749
750#if defined(SECURE_LITE2) && (defined(A18) || defined(REL23) || defined(REL29))
751        u16 SecondaryPid_p; /* passage support only */
752        u16 MainInfoSpare; /* SPARE REGISTER - ADDED FOR ALIGNMENT */
753#endif
754} TCMainInfo_t;
755
756typedef volatile struct TCInterruptDMAConfig_s
757{
758        u32 DMABase_p;
759        u32 DMATop_p;
760        u32 DMAWrite_p;
761        u32 DMARead_p;
762} TCInterruptDMAConfig_t;
763
764#if defined(REL29)
765#define STPTI_MAX_START_CODES_SUPPORTED 7
766
767typedef struct StartCode_s
768{
769        u8 Offset;
770        u8 Code;
771} StartCode_t;
772
773typedef volatile struct TCStatus_s
774{
775        u32 Flags;
776
777        u32 SlotError: 8;
778        u32 SlotNumber: 8;
779
780        u32 ExpectedCC: 4;
781        u32 ReceivedCC: 4;
782        u32 Odd_Even: 1;
783        u32 PESScrambled: 1;
784        u32 Scrambled: 1;
785        u32 ClearToScram: 1;
786        u32 Padding: 4;
787
788        u32 ArrivalTime0: 16;
789        u32 ArrivalTime1: 16;
790
791        u32 ArrivalTime2: 16;
792        u32 DMACtrl: 16;
793
794        u32 Pcr0: 16;
795        u32 Pcr1: 16;
796
797        u32 Pcr2: 16;
798        u32 NumberStartCodes: 8;
799        u32 PayloadLength: 8;
800
801        u32 BufferPacketNumber;
802        u32 BufferPacketOffset;
803        u32 RecordBufferPacketNumber;
804
805        u32 CarouselInfo;
806
807#if defined(SECURE_LITE2)
808        u32 StartCodePreviousBPN: 8;
809        u32 StartCodePreviousRecordBPN: 8;
810        StartCode_t StartCodes[STPTI_MAX_START_CODES_SUPPORTED];
811#endif
812
813} TCStatus_t;
814#elif defined(A18) || defined(REL23)
815
816#define STPTI_MAX_START_CODES_SUPPORTED 7
817
818typedef struct StartCode_s
819{
820        u8 Offset;
821        u8 Code;
822} StartCode_t;
823
824typedef volatile struct TCStatus_s
825{
826        u32 Flags;
827
828        u32 SlotError: 8;
829        u32 SlotNumber: 8;
830        u32 Odd_Even: 1;
831        u32 PESScrambled: 1;
832        u32 Scrambled: 1;
833#ifdef REL23
834        u32 ExpectedCC: 4;
835        u32 ReceivedCC: 4;
836        u32 Padding: 5;
837#else
838        u32 Padding: 13;
839#endif
840
841        u32 ArrivalTime0: 16;
842        u32 ArrivalTime1: 16;
843
844        u32 ArrivalTime2: 16;
845        u32 DMACtrl: 16;
846
847        u32 Pcr0: 16;
848        u32 Pcr1: 16;
849
850        u32 Pcr2: 16;
851        u32 NumberStartCodes: 8;
852        u32 PayloadLength: 8;
853
854        u32 BufferPacketNumber;
855        u32 BufferPacketOffset;
856        u32 RecordBufferPacketNumber;
857
858        u32 CarouselInfo;
859
860#if defined(SECURE_LITE2)
861        u32 StartCodePreviousBPN: 8;
862        u32 StartCodePreviousRecordBPN: 8;
863        StartCode_t StartCodes[STPTI_MAX_START_CODES_SUPPORTED];
864#endif
865
866} TCStatus_t;
867#else
868typedef volatile struct TCStatus_s
869{
870        u32 Flags;
871
872        u32 SlotError: 8;
873        u32 SlotNumber: 8;
874        u32 Odd_Even: 1;
875        u32 PESScrambled: 1;
876        u32 Scrambled: 1;
877        u32 Padding: 13;
878
879        u32 ArrivalTime0: 16;
880        u32 ArrivalTime1: 16;
881
882        u32 ArrivalTime2: 16;
883        u32 DMACtrl: 16;
884
885        u32 Pcr0: 16;
886        u32 Pcr1: 16;
887
888        u32 Pcr2: 16;
889        u32 NumberStartCodes: 8;
890        u32 PayloadLength: 8;
891
892        u32 BufferPacketNumber;
893        u32 BufferPacketOffset;
894        u32 RecordBufferPacketNumber;
895
896} TCStatus_t;
897#endif
898
899typedef volatile struct TCDMAConfig_s
900{
901        u32 DMABase_p;
902        u32 DMATop_p;
903        u32 DMAWrite_p;
904        u32 DMARead_p;
905        u32 DMAQWrite_p;
906        u32 BufferPacketCount;
907
908        u16 SignalModeFlags;
909        u16 Threshold;
910#if defined(SECURE_LITE2)
911        u16 BufferLevelThreshold;
912        u16 DMAConfig_Spare;
913#endif
914} TCDMAConfig_t;
915
916struct TCDMAConfigExt_s
917{
918        u32 BasePtr_physical;
919        u32 TopPtr_physical;
920        u8 *pBuf;
921        u32 bufSize;
922        u32 bufSize_sub_188;
923        u32 bufSize_div_188;
924        u32 bufSize_div_188_div_2;
925};
926
927/* Note that when writing host to TC the key undergoes an endian swap,
928this is more complex for the extended AES keys as they are split in 2 sections.
929Thus even keys 3:0 are effectively keys 7:4 for AES 16 byte keys... etc
930This maintains compatibility with 8 byte keys, and gives the simplest (fastest)
931TC access to the extended AES keys */
932
933typedef volatile struct TCKey_s
934{
935        u16 KeyValidity;
936        u16 KeyMode;
937
938        u16 EvenKey3;
939        u16 EvenKey2;
940
941        u16 EvenKey1;
942        u16 EvenKey0;
943
944        u16 OddKey3;
945        u16 OddKey2;
946
947        u16 OddKey1;
948        u16 OddKey0;
949        /* This is the end of the used portion for non-AES keys */
950
951        u16 EvenKey7;
952        u16 EvenKey6;
953        u16 EvenKey5;
954        u16 EvenKey4;
955
956        u16 EvenIV7;
957        u16 EvenIV6;
958        u16 EvenIV5;
959        u16 EvenIV4;
960        u16 EvenIV3;
961        u16 EvenIV2;
962        u16 EvenIV1;
963        u16 EvenIV0;
964
965        u16 OddKey7;
966        u16 OddKey6;
967        u16 OddKey5;
968        u16 OddKey4;
969
970        u16 OddIV7;
971        u16 OddIV6;
972        u16 OddIV5;
973        u16 OddIV4;
974        u16 OddIV3;
975        u16 OddIV2;
976        u16 OddIV1;
977        u16 OddIV0;
978
979} TCKey_t;
980
981#define TCKEY_VALIDITY_TS_EVEN 0x0001
982#define TCKEY_VALIDITY_TS_ODD 0x0002
983#define TCKEY_VALIDITY_PES_EVEN 0x0100
984#define TCKEY_VALIDITY_PES_ODD 0x0200
985
986#define TCKEY_ALGORITHM_DVB 0x0000
987#define TCKEY_ALGORITHM_DSS 0x1000
988#define TCKEY_ALGORITHM_FAST_I 0x2000
989#define TCKEY_ALGORITHM_AES 0x3000
990#define TCKEY_ALGORITHM_MULTI2 0x4000
991#define TCKEY_ALGORITHM_MASK 0xF000
992
993#define TCKEY_CHAIN_ALG_ECB 0x0000
994#define TCKEY_CHAIN_ALG_CBC 0x0010
995#define TCKEY_CHAIN_ALG_ECB_IV 0x0020
996#define TCKEY_CHAIN_ALG_CBC_IV 0x0030
997#define TCKEY_CHAIN_ALG_OFB 0x0040
998#define TCKEY_CHAIN_ALG_CTS 0x0050
999#define TCKEY_CHAIN_ALG_MASK 0x00F0
1000#define TCKEY_CHAIN_MODE_LR 0x0004
1001
1002#define TCKEY_MODE_EAVS 0x0001
1003#define TCKEY_MODE_PERM0 0x0004
1004#define TCKEY_MODE_PERM1 0x0006
1005#define TCKEY_MODE_ClearSCB 0x0010
1006#define TCKEY_MODE_MddnotMdi 0x0060
1007#define TCKEY_MODE_MSCDescrambling 0x0180
1008
1009/*
1010 Use for TCSectionFilterInfo_t
1011 TCSessionInfo_t
1012 TCMainInfo_t
1013 TCGlobalInfo_t
1014 TCKey_t
1015 TCDMAConfig_t
1016
1017 The TC registers definded in pti4.h that are u32:16 bit fields
1018 need be read modified and written back.
1019
1020 A single 16 bit write to ether the high or low part of a u32 is written
1021 to both the low and high parts.
1022
1023 So the unchanged part needs to be read and ORed with the changed part and
1024 written as a u32.
1025
1026 This function does just that.
1027
1028 It may not be the best way to do it but it works!!
1029*/
1030
1031/* This macro determines whether the write is to the high or low word.
1032 Reads in the complete 32 bit word writes in the high or low portion and
1033 then writes the whole word back.
1034 It get around the TC read modify write problem.
1035 This macro is a more efficient vertion of the macro below and the function
1036 below that. */
1037#define STSYS_WriteTCReg16LE( reg, u16value ) \
1038        { \
1039                u32 u32value = readl( (void*)((u32)(reg) & 0xfffffffC) );\
1040                *(u16*)((u32)&u32value + ((u32)(reg) & 0x02)) = (u16value);\
1041                writel(u32value, (void*)((u32)(reg) & 0xfffffffC) );\
1042        }
1043
1044/* Read the register and OR in the value and write it back. */
1045#define STSYS_SetTCMask16LE( reg, u16value)\
1046        {\
1047                STSYS_WriteTCReg16LE(reg, readw(reg) | u16value);\
1048        }
1049
1050/* Read the register and AND in the complement(~) of the value and write it back. */
1051#define STSYS_ClearTCMask16LE( reg, u16value)\
1052        {\
1053                STSYS_WriteTCReg16LE(reg, readw(reg) & ~u16value);\
1054        }
1055
1056#define GetTCData(ptr, x) { \
1057                u32 tmp; \
1058                STPTI_DevicePtr_t p; \
1059                if(((u32)(ptr) % 4) == 0) \
1060                { \
1061                        p = (STPTI_DevicePtr_t)(ptr); \
1062                        tmp = readl( (void*)p ); \
1063                } \
1064                else \
1065                { \
1066                        p = (STPTI_DevicePtr_t)((u32)(ptr) & ~0x3); \
1067                        tmp = readl( (void*)p ); \
1068                        tmp >>= 16; \
1069                } \
1070                tmp &= 0xffff; \
1071                (x) = tmp; \
1072        }
1073
1074#define PutTCData(ptr, x) { \
1075                u32 tmp; \
1076                STPTI_DevicePtr_t p; \
1077                if(((u32)(ptr) % 4) == 0) \
1078                { \
1079                        p = (STPTI_DevicePtr_t)(ptr); \
1080                        tmp = readl( (void*)p ); \
1081                        tmp &= 0xffff0000; \
1082                        tmp |= ((x)&0xffff); \
1083                } \
1084                else \
1085                { \
1086                        p = (STPTI_DevicePtr_t)((u32)(ptr) & ~0x3); \
1087                        tmp = readl( (void*)p ); \
1088                        tmp &= 0x0000ffff; \
1089                        tmp |= ((x)<<16); \
1090                } \
1091                writel( tmp, (void*)p ); \
1092        }
1093
1094extern irqreturn_t pti_interrupt_handler(int irq, void *data,
1095                                         struct pt_regs *regs);
1096
1097extern int pti_task(void *data);
1098
1099extern int debug ;
1100#define dprintk(x...) do { if (debug) printk(KERN_WARNING x); } while (0)
1101
1102#endif //_PTI_H_
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