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pti_main.c @ 45168

Last change on this file since 45168 was 45168, checked in by obi, 19 months ago
add oebuild building files
Property svn:executable set to ``*
File size: 29.5 KB

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1	#include <linux/init.h>
2	#include <linux/slab.h>
3	#include <linux/wait.h>
4	#include <linux/module.h>
5	#include <linux/usb.h>
6	#include <linux/delay.h>
7	#include <linux/time.h>
8	#include <linux/errno.h>
9
10	#include <linux/version.h>
11
12	#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,32)
13	#include <linux/semaphore.h>
14	#else
15	#include <asm/semaphore.h>
16	#endif
17	#include <linux/platform_device.h>
18	#include <linux/mutex.h>
19	#include <linux/dma-mapping.h>
20
21	#include <asm/io.h>
22
23	#if defined (CONFIG_KERNELVERSION) \|\| LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,32)
24	#include <linux/bpa2.h>
25	#else
26	#include <linux/bigphysarea.h>
27	#endif
28
29	#include "tc_code.h"
30	#include "pti.h"
31	#include "pti_public.h"
32
33	#ifdef WITH_CAMROUTING
34	int camRouting = 0;
35	#endif
36
37	int debug = 0;
38
39	/* video memory in dvb packets */
40	#ifdef UFS910
41	int videoMem = 2048;
42	#else
43	int videoMem = 4096;
44	#endif
45
46	/* waiting time in ms for wait queue in pti_prcoess.c */
47	int waitMS = 20;
48
49	#ifdef CONFIG_PRINTK
50	/* enable statistic output on pti */
51	int enableStatistic = 0;
52	#else
53	int enableSysStatistic = 1;
54
55	unsigned long pti_last_time = 0;
56	unsigned long pti_count = 0;
57	#endif
58
59	static void stpti_MemoryAlign(void Memory_p, u32 Alignment)
60	{
61	return (void *)((u32)((u32)Memory_p + Alignment - 1) & ~(Alignment - 1));
62	}
63
64	static size_t stpti_BufferSizeAdjust(size_t Size)
65	{
66	return ((size_t)stpti_MemoryAlign((void *)Size, STPTI_BUFFER_SIZE_MULTIPLE));
67	}
68
69	static void stpti_BufferBaseAdjust(void Base_p)
70	{
71	return (stpti_MemoryAlign(Base_p, STPTI_BUFFER_ALIGN_MULTIPLE));
72	}
73
74	/* *****************************
75	* Global vars
76	*/
77	TCDevice_t *myTC = NULL;
78	STPTI_TCParameters_t tc_params;
79
80	#define STSYS_WriteRegDev32LE(a, b) writel(b,a)
81	#define STSYS_ReadRegDev32LE(x) readl(x)
82
83	static void stopTc(TCDevice_t *TC_Device)
84	{
85	STSYS_WriteRegDev32LE((void )&TC_Device->IIFFIFOEnable, 0x00); / Stop the IIF */
86	STSYS_WriteRegDev32LE((void )&TC_Device->TCMode, 0x00); / Stop the TC */
87	/* --- Perform a software reset --- */
88	STSYS_WriteRegDev32LE((void )&TC_Device->DMAPTI3Prog, 0x01); / PTI3 Mode */
89	STSYS_WriteRegDev32LE((void )&TC_Device->DMAFlush, 0x01); / Flush DMA 0 */
90	/* For PTI4SL, if we do not enable the DMA here, the flush never occurs... */
91	STSYS_WriteRegDev32LE((void )&TC_Device->DMAEnable, 0x01); / Enable the DMA */
92	while (STSYS_ReadRegDev32LE((void *)&TC_Device->DMAFlush) & 0X01)
93	udelay(100 * 64); /* 6400us */
94	STSYS_WriteRegDev32LE((void )&TC_Device->TCMode, 0x08); / Full Reset the TC */
95	udelay(200 * 64); /* 12800us / / Wait */
96	STSYS_WriteRegDev32LE((void )&TC_Device->TCMode, 0x00); / Finish Full Reset the TC */
97	udelay(10 * 64); /* 640us */
98	}
99
100	/* ************************************
101	* From InitializeDevice in basic.c
102	* the TC is only for pti4 otherwise
103	* another loader should be used
104	*/
105	void pti_main_loadtc(struct stpti *pti)
106	{
107	STPTI_DevicePtr_t CodeStart;
108	TCDevice_t *TC_Device;
109	u16 IIFSyncPeriod;
110	u16 TagBytes;
111	u32 PTI4_Base, i;
112	TCGlobalInfo_t *TCGlobalInfo;
113	static u8 DmaFifoFlushingTarget[188 + DMAScratchAreaSize];
114	int session; /* Initialize session info structures */
115	u8 *base_p;
116	u8 *top_p;
117	size_t DMABufferSize = 0;
118	int block, index;
119	TCSectionFilterArrays_t *TC_SectionFilterArrays_p;
120	STPTI_TCParameters_t *TC_Params_p;
121	TCInterruptDMAConfig_t *TCInterruptDMAConfig_p;
122	myTC = (TCDevice_t *) pti->pti_io;
123	CodeStart = &myTC->TC_Code[0];
124	PTI4_Base = (u32)((u32)CodeStart - 0XC000);
125	TC_Params_p = &tc_params;
126	ioremap_nocache((unsigned long)&myTC, sizeof(TCDevice_t));
127	stopTc(myTC);
128	// *********************************
129	//Load TC
130	printk("Load real TC Code\n");
131	printk("TC_Data = %p, TC_Code = %p\n", myTC->TC_Data, myTC->TC_Code);
132	TC_Params_p->TC_CodeStart = (STPTI_DevicePtr_t)VERSION;
133	TC_Params_p->TC_CodeStart = CodeStart;
134	TC_Params_p->TC_CodeSize = TRANSPORT_CONTROLLER_CODE_SIZE * sizeof(u32);
135	TC_Params_p->TC_DataStart = (u32 *)(((u32)PTI4_Base) + 0X8000);
136	#if (defined (CONFIG_CPU_SUBTYPE_STX7111) \|\| defined (CONFIG_CPU_SUBTYPE_STX7105)) && defined(SECURE_LITE2) && defined(REL29)
137	TC_Params_p->TC_LookupTableStart = (u32 *)(((u32)PTI4_Base) + 0X8000);
138	TC_Params_p->TC_SystemKeyStart = (u32 *)(((u32)PTI4_Base) + 0X8100);
139	TC_Params_p->TC_GlobalDataStart = (u32 *)(((u32)PTI4_Base) + 0X8464);
140	TC_Params_p->TC_StatusBlockStart = (u32 *)(((u32)PTI4_Base) + 0X84B8);
141	TC_Params_p->TC_MainInfoStart = (u32 *)(((u32)PTI4_Base) + 0X84F0);
142	TC_Params_p->TC_DMAConfigStart = (u32 *)(((u32)PTI4_Base) + 0X90F0);
143	TC_Params_p->TC_DescramblerKeysStart = (u32 *)(((u32)PTI4_Base) + 0X97D0);
144	TC_Params_p->TC_TransportFilterStart = (u32 *)(((u32)PTI4_Base) + 0X9E74);
145	TC_Params_p->TC_SCDFilterTableStart = (u32 *)(((u32)PTI4_Base) + 0X9E74);
146	TC_Params_p->TC_PESFilterStart = (u32 *)(((u32)PTI4_Base) + 0X9F34);
147	TC_Params_p->TC_SubstituteDataStart = (u32 *)(((u32)PTI4_Base) + 0X8120);
148	TC_Params_p->TC_SFStatusStart = (u32 *)(((u32)PTI4_Base) + 0X9F34);
149	TC_Params_p->TC_InterruptDMAConfigStart = (u32 *)(((u32)PTI4_Base) + 0XB334);
150	TC_Params_p->TC_SessionDataStart = (u32 *)(((u32)PTI4_Base) + 0XB344);
151	TC_Params_p->TC_EMMStart = (u32 *)(((u32)PTI4_Base) + 0XB4FC);
152	TC_Params_p->TC_ECMStart = (u32 *)(((u32)PTI4_Base) + 0XB4FC);
153	TC_Params_p->TC_VersionID = (u32 *)(((u32)PTI4_Base) + 0XB558);
154	TC_Params_p->TC_NumberCarousels = 0X0001;
155	TC_Params_p->TC_NumberSystemKeys = 0X0001;
156	TC_Params_p->TC_NumberDMAs = 0X0037;
157	TC_Params_p->TC_NumberDescramblerKeys = 0X0019;
158	TC_Params_p->TC_SizeOfDescramblerKeys = 0X0044;
159	TC_Params_p->TC_NumberPesFilters = 0X0000;
160	TC_Params_p->TC_NumberSectionFilters = 0X0080;
161	TC_Params_p->TC_NumberSlots = 0X0080;
162	TC_Params_p->TC_NumberOfSessions = 0X0005;
163	TC_Params_p->TC_NumberIndexs = 0X0080;
164	TC_Params_p->TC_NumberTransportFilters = 0X0000;
165	TC_Params_p->TC_NumberSCDFilters = 0X0018;
166	TC_Params_p->TC_SignalEveryTransportPacket = 0X0001;
167	TC_Params_p->TC_NumberEMMFilters = 0X0000;
168	TC_Params_p->TC_SizeOfEMMFilter = 0X001C;
169	TC_Params_p->TC_NumberECMFilters = 0X0080;
170	TC_Params_p->TC_AutomaticSectionFiltering = FALSE;
171	{
172	STPTI_DevicePtr_t DataStart = (u32 *)(((u32)CodeStart & 0xffff0000) \| 0X8000);
173	for (i = 0; i < (0X3800 / 4); ++i)
174	{
175	writel(0x00 , (u32)&DataStart[i]);
176	}
177	for (i = 0; i < 0X1000; ++i)
178	{
179	writel(0x00 , (u32)&CodeStart[i]);
180	}
181	for (i = 0; i < TRANSPORT_CONTROLLER_CODE_SIZE; ++i)
182	{
183	writel(transport_controller_code[i], (u32)&CodeStart[i]);
184	}
185	writel(0X5354 \| (0X5054 << 16), (u32) & (TC_Params_p->TC_VersionID[0]));
186	writel(0X4934 \| (0X001F << 16), (u32) & (TC_Params_p->TC_VersionID[1]));
187	writel(0x0019 \| (0X0000 << 16), (u32) & (TC_Params_p->TC_VersionID[2]));
188	printk("Readback TC ... ");
189	for (i = 0; i < TRANSPORT_CONTROLLER_CODE_SIZE; ++i)
190	{
191	unsigned long res = readl((u32)&CodeStart[i]);
192	if (res != transport_controller_code[i])
193	{
194	printk("failed !!!!\n");
195	break;
196	}
197	}
198	if (i == TRANSPORT_CONTROLLER_CODE_SIZE)
199	{
200	printk("successfull\n");
201	}
202	}
203	#elif (defined (CONFIG_CPU_SUBTYPE_STX7111) \|\| defined (CONFIG_CPU_SUBTYPE_STX7105)) && defined(SECURE_LITE2) && defined(REL23)
204	TC_Params_p->TC_LookupTableStart = (u32 *)(((u32)PTI4_Base) + 0X8000);
205	TC_Params_p->TC_SystemKeyStart = (u32 *)(((u32)PTI4_Base) + 0X8100);
206	TC_Params_p->TC_GlobalDataStart = (u32 *)(((u32)PTI4_Base) + 0X8464);
207	TC_Params_p->TC_StatusBlockStart = (u32 *)(((u32)PTI4_Base) + 0X84BC);
208	TC_Params_p->TC_MainInfoStart = (u32 *)(((u32)PTI4_Base) + 0X84F4);
209	TC_Params_p->TC_DMAConfigStart = (u32 *)(((u32)PTI4_Base) + 0X90F4);
210	TC_Params_p->TC_DescramblerKeysStart = (u32 *)(((u32)PTI4_Base) + 0X97D4);
211	TC_Params_p->TC_TransportFilterStart = (u32 *)(((u32)PTI4_Base) + 0X9E78);
212	TC_Params_p->TC_SCDFilterTableStart = (u32 *)(((u32)PTI4_Base) + 0X9E78);
213	TC_Params_p->TC_PESFilterStart = (u32 *)(((u32)PTI4_Base) + 0X9F38);
214	TC_Params_p->TC_SubstituteDataStart = (u32 *)(((u32)PTI4_Base) + 0X8120);
215	TC_Params_p->TC_SFStatusStart = (u32 *)(((u32)PTI4_Base) + 0X9F38);
216	TC_Params_p->TC_InterruptDMAConfigStart = (u32 *)(((u32)PTI4_Base) + 0XB338);
217	TC_Params_p->TC_SessionDataStart = (u32 *)(((u32)PTI4_Base) + 0XB348);
218	TC_Params_p->TC_EMMStart = (u32 *)(((u32)PTI4_Base) + 0XB500);
219	TC_Params_p->TC_ECMStart = (u32 *)(((u32)PTI4_Base) + 0XB500);
220	TC_Params_p->TC_VersionID = (u32 *)(((u32)PTI4_Base) + 0XB540);
221	TC_Params_p->TC_NumberCarousels = 0X0001;
222	TC_Params_p->TC_NumberSystemKeys = 0X0001;
223	TC_Params_p->TC_NumberDMAs = 0X0037;
224	TC_Params_p->TC_NumberDescramblerKeys = 0X0019;
225	TC_Params_p->TC_SizeOfDescramblerKeys = 0X0044;
226	TC_Params_p->TC_NumberPesFilters = 0X0000;
227	TC_Params_p->TC_NumberSectionFilters = 0X0080;
228	TC_Params_p->TC_NumberSlots = 0X0080;
229	TC_Params_p->TC_NumberOfSessions = 0X0005;
230	TC_Params_p->TC_NumberIndexs = 0X0080;
231	TC_Params_p->TC_NumberTransportFilters = 0X0000;
232	TC_Params_p->TC_NumberSCDFilters = 0X0018;
233	TC_Params_p->TC_SignalEveryTransportPacket = 0X0001;
234	TC_Params_p->TC_NumberEMMFilters = 0X0000;
235	TC_Params_p->TC_SizeOfEMMFilter = 0X001C;
236	TC_Params_p->TC_NumberECMFilters = 0X0080;
237	TC_Params_p->TC_AutomaticSectionFiltering = FALSE;
238	{
239	STPTI_DevicePtr_t DataStart = (u32 *)(((u32)CodeStart & 0xffff0000) \| 0X8000);
240	for (i = 0; i < (0X3800 / 4); ++i)
241	{
242	writel(0x00 , (u32)&DataStart[i]);
243	}
244	for (i = 0; i < 0X1000; ++i)
245	{
246	writel(0x00 , (u32)&CodeStart[i]);
247	}
248	for (i = 0; i < TRANSPORT_CONTROLLER_CODE_SIZE; ++i)
249	{
250	writel(transport_controller_code[i], (u32)&CodeStart[i]);
251	}
252	writel(0X5354 \| (0X5054 << 16), (u32) & (TC_Params_p->TC_VersionID[0]));
253	writel(0X4934 \| (0X001F << 16), (u32) & (TC_Params_p->TC_VersionID[1]));
254	writel(0x000F \| (0X0000 << 16), (u32) & (TC_Params_p->TC_VersionID[2]));
255	printk("Readback TC ... ");
256	for (i = 0; i < TRANSPORT_CONTROLLER_CODE_SIZE; ++i)
257	{
258	unsigned long res = readl((u32)&CodeStart[i]);
259	if (res != transport_controller_code[i])
260	{
261	printk("failed !!!!\n");
262	break;
263	}
264	}
265	if (i == TRANSPORT_CONTROLLER_CODE_SIZE)
266	{
267	printk("successfull\n");
268	}
269	}
270	#elif (defined (CONFIG_CPU_SUBTYPE_STX7111) \|\| defined (CONFIG_CPU_SUBTYPE_STX7105)) && defined(SECURE_LITE2) && defined(A18)
271	TC_Params_p->TC_LookupTableStart = (u32 *)(((u32)PTI4_Base) + 0X8000);
272	TC_Params_p->TC_SystemKeyStart = (u32 *)(((u32)PTI4_Base) + 0X80C0);
273	TC_Params_p->TC_GlobalDataStart = (u32 *)(((u32)PTI4_Base) + 0X850C);
274	TC_Params_p->TC_StatusBlockStart = (u32 *)(((u32)PTI4_Base) + 0X8560);
275	TC_Params_p->TC_MainInfoStart = (u32 *)(((u32)PTI4_Base) + 0X8598);
276	TC_Params_p->TC_DMAConfigStart = (u32 *)(((u32)PTI4_Base) + 0X8E98);
277	TC_Params_p->TC_DescramblerKeysStart = (u32 *)(((u32)PTI4_Base) + 0X9578);
278	TC_Params_p->TC_TransportFilterStart = (u32 *)(((u32)PTI4_Base) + 0X9C1C);
279	TC_Params_p->TC_SCDFilterTableStart = (u32 *)(((u32)PTI4_Base) + 0X9C1C);
280	TC_Params_p->TC_PESFilterStart = (u32 *)(((u32)PTI4_Base) + 0X9CDC);
281	TC_Params_p->TC_SubstituteDataStart = (u32 *)(((u32)PTI4_Base) + 0X81C8);
282	TC_Params_p->TC_SFStatusStart = (u32 *)(((u32)PTI4_Base) + 0X9CDC);
283	TC_Params_p->TC_InterruptDMAConfigStart = (u32 *)(((u32)PTI4_Base) + 0XB0DC);
284	TC_Params_p->TC_SessionDataStart = (u32 *)(((u32)PTI4_Base) + 0XB0EC);
285	TC_Params_p->TC_EMMStart = (u32 *)(((u32)PTI4_Base) + 0XB2A4);
286	TC_Params_p->TC_ECMStart = (u32 *)(((u32)PTI4_Base) + 0XB2A4);
287	TC_Params_p->TC_VersionID = (u32 *)(((u32)PTI4_Base) + 0XB2E4);
288	TC_Params_p->TC_NumberCarousels = 0X0001;
289	TC_Params_p->TC_NumberSystemKeys = 0X0001;
290	TC_Params_p->TC_NumberDMAs = 0X0037;
291	TC_Params_p->TC_NumberDescramblerKeys = 0X0019;
292	TC_Params_p->TC_SizeOfDescramblerKeys = 0X0044;
293	TC_Params_p->TC_NumberPesFilters = 0X0000;
294	TC_Params_p->TC_NumberSectionFilters = 0X0080;
295	TC_Params_p->TC_NumberSlots = 0X0060;
296	TC_Params_p->TC_NumberOfSessions = 0X0005;
297	TC_Params_p->TC_NumberIndexs = 0X0060;
298	TC_Params_p->TC_NumberTransportFilters = 0X0000;
299	TC_Params_p->TC_NumberSCDFilters = 0X0018;
300	TC_Params_p->TC_SignalEveryTransportPacket = 0X0001;
301	TC_Params_p->TC_NumberEMMFilters = 0X0000;
302	TC_Params_p->TC_SizeOfEMMFilter = 0X001C;
303	TC_Params_p->TC_NumberECMFilters = 0X0060;
304	TC_Params_p->TC_AutomaticSectionFiltering = FALSE;
305	{
306	STPTI_DevicePtr_t DataStart = (u32 *)(((u32)CodeStart & 0xffff0000) \| 0X8000);
307	for (i = 0; i < (0X3800 / 4); ++i)
308	{
309	writel(0x00 , (u32)&DataStart[i]);
310	}
311	for (i = 0; i < 0X1000; ++i)
312	{
313	writel(0x00 , (u32)&CodeStart[i]);
314	}
315	for (i = 0; i < TRANSPORT_CONTROLLER_CODE_SIZE; ++i)
316	{
317	writel(transport_controller_code[i], (u32)&CodeStart[i]);
318	}
319	writel(0X5354 \| (0X5054 << 16), (u32) & (TC_Params_p->TC_VersionID[0]));
320	writel(0X4934 \| (0X001F << 16), (u32) & (TC_Params_p->TC_VersionID[1]));
321	writel(0X0803 \| (0X0000 << 16), (u32) & (TC_Params_p->TC_VersionID[2]));
322	printk("Readback TC ... ");
323	for (i = 0; i < TRANSPORT_CONTROLLER_CODE_SIZE; ++i)
324	{
325	unsigned long res = readl((u32)&CodeStart[i]);
326	if (res != transport_controller_code[i])
327	{
328	printk("failed !!!!\n");
329	break;
330	}
331	}
332	if (i == TRANSPORT_CONTROLLER_CODE_SIZE)
333	{
334	printk("successfull\n");
335	}
336	}
337	#elif defined(A18)
338	TC_Params_p->TC_LookupTableStart = (u32 *)(((u32)PTI4_Base) + 0X8000);
339	TC_Params_p->TC_SystemKeyStart = (u32 *)(((u32)PTI4_Base) + 0X80C0);
340	TC_Params_p->TC_GlobalDataStart = (u32 *)(((u32)PTI4_Base) + 0X8270);
341	TC_Params_p->TC_StatusBlockStart = (u32 *)(((u32)PTI4_Base) + 0X82B8);
342	TC_Params_p->TC_MainInfoStart = (u32 *)(((u32)PTI4_Base) + 0X82E0);
343	TC_Params_p->TC_DMAConfigStart = (u32 *)(((u32)PTI4_Base) + 0X8A60);
344	TC_Params_p->TC_DescramblerKeysStart = (u32 *)(((u32)PTI4_Base) + 0X902C);
345	TC_Params_p->TC_TransportFilterStart = (u32 *)(((u32)PTI4_Base) + 0X9194);
346	TC_Params_p->TC_SCDFilterTableStart = (u32 *)(((u32)PTI4_Base) + 0X9194);
347	TC_Params_p->TC_PESFilterStart = (u32 *)(((u32)PTI4_Base) + 0X9194);
348	TC_Params_p->TC_SubstituteDataStart = (u32 *)(((u32)PTI4_Base) + 0X81A8);
349	TC_Params_p->TC_SFStatusStart = (u32 *)(((u32)PTI4_Base) + 0X9194);
350	TC_Params_p->TC_InterruptDMAConfigStart = (u32 *)(((u32)PTI4_Base) + 0X9894);
351	TC_Params_p->TC_SessionDataStart = (u32 *)(((u32)PTI4_Base) + 0X98A4);
352	TC_Params_p->TC_EMMStart = (u32 *)(((u32)PTI4_Base) + 0X9970);
353	TC_Params_p->TC_ECMStart = (u32 *)(((u32)PTI4_Base) + 0X9970);
354	TC_Params_p->TC_VersionID = (u32 *)(((u32)PTI4_Base) + 0X9970);
355	TC_Params_p->TC_NumberCarousels = 0X0001;
356	TC_Params_p->TC_NumberSystemKeys = 0X0000;
357	TC_Params_p->TC_NumberDMAs = 0X0035;
358	TC_Params_p->TC_NumberDescramblerKeys = 0X0012;
359	TC_Params_p->TC_SizeOfDescramblerKeys = 0X0014;
360	TC_Params_p->TC_NumberPesFilters = 0X0000;
361	TC_Params_p->TC_NumberSectionFilters = 0X0040;
362	TC_Params_p->TC_NumberSlots = 0X0060;
363	TC_Params_p->TC_NumberOfSessions = 0X0003;
364	TC_Params_p->TC_NumberIndexs = 0X0060;
365	TC_Params_p->TC_NumberTransportFilters = 0X0000;
366	TC_Params_p->TC_NumberSCDFilters = 0X0000;
367	TC_Params_p->TC_SignalEveryTransportPacket = 0X0001;
368	TC_Params_p->TC_NumberEMMFilters = 0X0000;
369	TC_Params_p->TC_SizeOfEMMFilter = 0X001C;
370	TC_Params_p->TC_NumberECMFilters = 0X0060;
371	TC_Params_p->TC_AutomaticSectionFiltering = FALSE;
372	{
373	STPTI_DevicePtr_t DataStart = (u32 *)(((u32)CodeStart & 0xffff0000) \| 0X8000);
374	for (i = 0; i < (0X1A00 / 4); ++i)
375	{
376	writel(0x00 , (u32)&DataStart[i]);
377	}
378	for (i = 0; i < 0X0780; ++i)
379	{
380	writel(0x00 , (u32)&CodeStart[i]);
381	}
382	for (i = 0; i < TRANSPORT_CONTROLLER_CODE_SIZE; ++i)
383	{
384	writel(transport_controller_code[i], (u32)&CodeStart[i]);
385	}
386	writel(0X5354 \| (0X5054 << 16), (u32) & (TC_Params_p->TC_VersionID[0]));
387	writel(0X4934 \| (0X0000 << 16), (u32) & (TC_Params_p->TC_VersionID[1]));
388	writel(0X0803 \| (0X0000 << 16), (u32) & (TC_Params_p->TC_VersionID[2]));
389	printk("Readback TC ... ");
390	for (i = 0; i < TRANSPORT_CONTROLLER_CODE_SIZE; ++i)
391	{
392	unsigned long res = readl((u32)&CodeStart[i]);
393	if (res != transport_controller_code[i])
394	{
395	printk("failed !!!!\n");
396	break;
397	}
398	}
399	if (i == TRANSPORT_CONTROLLER_CODE_SIZE)
400	{
401	printk("successfull\n");
402	}
403	}
404	#else
405	TC_Params_p->TC_LookupTableStart = (u32 *)(((u32)PTI4_Base) + 0X8000);
406	TC_Params_p->TC_SystemKeyStart = (u32 *)(((u32)PTI4_Base) + 0X80C0);
407	TC_Params_p->TC_GlobalDataStart = (u32 *)(((u32)PTI4_Base) + 0X826C);
408	TC_Params_p->TC_StatusBlockStart = (u32 *)(((u32)PTI4_Base) + 0X82B4);
409	TC_Params_p->TC_MainInfoStart = (u32 *)(((u32)PTI4_Base) + 0X82D8);
410	TC_Params_p->TC_DMAConfigStart = (u32 *)(((u32)PTI4_Base) + 0X8A58);
411	TC_Params_p->TC_DescramblerKeysStart = (u32 *)(((u32)PTI4_Base) + 0X905C);
412	TC_Params_p->TC_TransportFilterStart = (u32 *)(((u32)PTI4_Base) + 0X91C4);
413	TC_Params_p->TC_SCDFilterTableStart = (u32 *)(((u32)PTI4_Base) + 0X91C4);
414	TC_Params_p->TC_PESFilterStart = (u32 *)(((u32)PTI4_Base) + 0X91C4);
415	TC_Params_p->TC_SubstituteDataStart = (u32 *)(((u32)PTI4_Base) + 0X81A8);
416	TC_Params_p->TC_SFStatusStart = (u32 *)(((u32)PTI4_Base) + 0X91C4);
417	TC_Params_p->TC_InterruptDMAConfigStart = (u32 *)(((u32)PTI4_Base) + 0X98C4);
418	TC_Params_p->TC_SessionDataStart = (u32 *)(((u32)PTI4_Base) + 0X98D4);
419	TC_Params_p->TC_EMMStart = (u32 *)(((u32)PTI4_Base) + 0X9994);
420	TC_Params_p->TC_ECMStart = (u32 *)(((u32)PTI4_Base) + 0X9994);
421	TC_Params_p->TC_VersionID = (u32 *)(((u32)PTI4_Base) + 0X99B4);
422	TC_Params_p->TC_NumberCarousels = 0X0001;
423	TC_Params_p->TC_NumberSystemKeys = 0X0000;
424	TC_Params_p->TC_NumberDMAs = 0X0037;
425	TC_Params_p->TC_NumberDescramblerKeys = 0X0012;
426	TC_Params_p->TC_SizeOfDescramblerKeys = 0X0014;
427	TC_Params_p->TC_NumberPesFilters = 0X0000;
428	TC_Params_p->TC_NumberSectionFilters = 0X0040;
429	TC_Params_p->TC_NumberSlots = 0X0060;
430	TC_Params_p->TC_NumberOfSessions = 0X0003;
431	TC_Params_p->TC_NumberIndexs = 0X0060;
432	TC_Params_p->TC_NumberTransportFilters = 0X0000;
433	TC_Params_p->TC_NumberSCDFilters = 0X0000;
434	TC_Params_p->TC_SignalEveryTransportPacket = 0X0001;
435	TC_Params_p->TC_NumberEMMFilters = 0X0000;
436	TC_Params_p->TC_NumberECMFilters = 0X0060;
437	TC_Params_p->TC_AutomaticSectionFiltering = FALSE;
438	{
439	STPTI_DevicePtr_t DataStart = (u32 *)(((u32)CodeStart & 0xffff0000) \| 0X8000);
440	for (i = 0; i < (0X1A00 / 4); ++i)
441	{
442	writel(0x00 , (u32)&DataStart[i]);
443	}
444	for (i = 0; i < 0X0900; ++i)
445	{
446	writel(0x00 , (u32)&CodeStart[i]);
447	}
448	for (i = 0; i < TRANSPORT_CONTROLLER_CODE_SIZE; ++i)
449	{
450	writel(transport_controller_code[i], (u32)&CodeStart[i]);
451	}
452	writel(0X5354 \| (0X5054 << 16), (u32) & (TC_Params_p->TC_VersionID[0]));
453	writel(0X4934 \| (0X0000 << 16), (u32) & (TC_Params_p->TC_VersionID[1]));
454	writel(0X84D0 \| (0X0000 << 16), (u32) & (TC_Params_p->TC_VersionID[2]));
455	printk("Readback TC ... ");
456	for (i = 0; i < TRANSPORT_CONTROLLER_CODE_SIZE; ++i)
457	{
458	unsigned long res = readl((u32)&CodeStart[i]);
459	if (res != transport_controller_code[i])
460	{
461	printk("failed !!!!\n");
462	break;
463	}
464	}
465	if (i == TRANSPORT_CONTROLLER_CODE_SIZE)
466	{
467	printk("successfull\n");
468	}
469	}
470	#endif
471	//stopTc(myTC);
472	//Load TC
473	// *********************************
474	// *********************************
475	//Init Hardware (stptiHelper_TCInit_Hardware)
476	TC_Device = myTC;
477	IIFSyncPeriod = 188 /* DVB_TS_PACKET_LENGTH/; / default is 188 for DVB */
478	TagBytes = 0; /* default is TSMERGER in bypass mode (or no TSMERGER) */
479	/* --- Initialize TC registers --- */
480	writel(0 , (void *)&TC_Device->TCMode);
481	writel(0xffff, (void *)&TC_Device->PTIIntAck0);
482	writel(0xffff, (void *)&TC_Device->PTIIntAck1);
483	writel(0xffff, (void *)&TC_Device->PTIIntAck2);
484	writel(0xffff, (void *)&TC_Device->PTIIntAck3);
485	/* disable all interrupts */
486	writel(0 , (void *)&TC_Device->PTIIntEnable0);
487	writel(0 , (void *)&TC_Device->PTIIntEnable1);
488	writel(0 , (void *)&TC_Device->PTIIntEnable2);
489	writel(0 , (void *)&TC_Device->PTIIntEnable3);
490	/* Initialise various registers */
491	writel(0 , (void *)&TC_Device->STCTimer0);
492	writel(0 , (void *)&TC_Device->STCTimer1);
493	/* Initialise DMA Registers */
494	writel(0 , (void )&TC_Device->DMAEnable); / Disable DMAs */
495	writel(1 , (void )&TC_Device->DMAPTI3Prog); / PTI3 Mode */
496	writel(0 , (void *)&TC_Device->DMA0Base);
497	writel(0 , (void *)&TC_Device->DMA0Top);
498	writel(0 , (void *)&TC_Device->DMA0Write);
499	writel(0 , (void *)&TC_Device->DMA0Read);
500	writel(0 , (void *)&TC_Device->DMA0Setup);
501	writel((1 \| (1 << 16)), (void *)&TC_Device->DMA0Holdoff);
502	writel(0 , (void *)&TC_Device->DMA0Status);
503	writel(0 , (void *)&TC_Device->DMA1Base);
504	writel(0 , (void *)&TC_Device->DMA1Top);
505	writel(0 , (void *)&TC_Device->DMA1Write);
506	writel(0 , (void *)&TC_Device->DMA1Read);
507	writel(0 , (void *)&TC_Device->DMA1Setup);
508	writel((1 \| (1 << 16)) , (void *)&TC_Device->DMA1Holdoff);
509	writel(0 , (void *)&TC_Device->DMA1CDAddr);
510	writel(0 , (void *)&TC_Device->DMASecStart);
511	writel(0 , (void *)&TC_Device->DMA2Base);
512	writel(0 , (void *)&TC_Device->DMA2Top);
513	writel(0 , (void *)&TC_Device->DMA2Write);
514	writel(0 , (void *)&TC_Device->DMA2Read);
515	writel(0 , (void *)&TC_Device->DMA2Setup);
516	writel((1 \| (1 << 16)), (void *)&TC_Device->DMA2Holdoff);
517	writel(0 , (void *)&TC_Device->DMA2CDAddr);
518	writel(0 , (void *)&TC_Device->DMAFlush);
519	writel(0 , (void *)&TC_Device->DMA3Base);
520	writel(0 , (void *)&TC_Device->DMA3Top);
521	writel(0 , (void *)&TC_Device->DMA3Write);
522	writel(0 , (void *)&TC_Device->DMA3Read);
523	writel(0 , (void *)&TC_Device->DMA3Setup);
524	writel((1 \| (1 << 16)), (void *)&TC_Device->DMA3Holdoff);
525	writel(0 , (void *)&TC_Device->DMA3CDAddr);
526	writel(0xf , (void )&TC_Device->DMAEnable); / Enable DMAs */
527	/* Initialise IIF Registers */
528	writel(0 , (void *)&TC_Device->IIFFIFOEnable);
529	writel(1/Device_p->AlternateOutputLatency/ , (void *)&TC_Device->IIFAltLatency);
530	writel(0/Device_p->SyncLock/, (void *)&TC_Device->IIFSyncLock);
531	writel(0/Device_p->SyncDrop/, (void *)&TC_Device->IIFSyncDrop);
532	writel(IIF_SYNC_CONFIG_USE_SOP , (void *)&TC_Device->IIFSyncConfig);
533	TagBytes = 6;
534	writel(IIFSyncPeriod + TagBytes , (void *)&TC_Device->IIFSyncPeriod);
535	writel(1 , (void *)&TC_Device->IIFCAMode);
536	//Init Hardware
537	// *********************************
538	// *********************************************************
539	//Init PidSearchEngine (stptiHelper_TCInit_PidSearchEngine)
540	for (i = 0; i < TC_Params_p->TC_NumberSlots; i++)
541	{
542	volatile u16 Addr_p = (volatile u16 ) TC_Params_p->TC_LookupTableStart;
543	PutTCData(&Addr_p[i], TC_INVALID_PID);
544	}
545	//Init PidSearchEngine (stptiHelper_TCInit_PidSearchEngine)
546	// *********************************************************
547	// *****************************************
548	//Init GlobalInfo (stptiHelper_TCInit_GlobalInfo)
549	TCGlobalInfo = (TCGlobalInfo_t *)TC_Params_p->TC_GlobalDataStart;
550	/* Set the scratch area so TC can dump DMA0 data (in cdfifo-ish mode). Be paranoid
551	and set the buffer to a DVB packet plus alignment/guard bytes */
552	writel((((u32)(DmaFifoFlushingTarget)) + 15) & (~0x0f) , (void *)&TCGlobalInfo->GlobalScratch);
553	STSYS_WriteTCReg16LE((void )&TCGlobalInfo->GlobalSFTimeout, 1429); / default is 1429 iterations * 7 tc cycles = 10003 tc cycles */
554	//Init GlobalInfo (stptiHelper_TCInit_GlobalInfo)
555	// *****************************************
556	// ******************************************
557	//Init MainInfo (stptiHelper_TCInit_MainInfo)
558	for (i = 0; i < TC_Params_p->TC_NumberSlots; i++)
559	{
560	TCMainInfo_t MainInfo = &((TCMainInfo_t ) TC_Params_p->TC_MainInfoStart)[i];
561	STSYS_WriteTCReg16LE((void *)&MainInfo->SlotState, 0);
562	STSYS_WriteTCReg16LE((void *)&MainInfo->SlotMode, 0);
563	STSYS_WriteTCReg16LE((void *)&MainInfo->DescramblerKeys_p, TC_INVALID_LINK);
564	STSYS_WriteTCReg16LE((void *)&MainInfo->DMACtrl_indices, 0xFFFF);
565	STSYS_WriteTCReg16LE((void *)&MainInfo->StartCodeIndexing_p, 0);
566	STSYS_WriteTCReg16LE((void *)&MainInfo->SectionPesFilter_p, TC_INVALID_LINK);
567	STSYS_WriteTCReg16LE((void *)&MainInfo->RemainingPESLength, 0);
568	STSYS_WriteTCReg16LE((void *)&MainInfo->PacketCount, 0);
569	STSYS_WriteTCReg16LE((void *)&MainInfo->SlotState, 0);
570	STSYS_WriteTCReg16LE((void *)&MainInfo->SlotMode, 0);
571	}
572	//Init MainInfo (stptiHelper_TCInit_MainInfo)
573	// ******************************************
574	// ******************************************
575	//Init SessionInfo (stptiHelper_TCInit_SessionInfo)
576	for (session = 0; session < TC_Params_p->TC_NumberOfSessions; session++)
577	{
578	TCSessionInfo_t SessionInfo_p = &((TCSessionInfo_t ) TC_Params_p->TC_SessionDataStart)[session];
579	STSYS_WriteTCReg16LE((void *)&SessionInfo_p->SessionTSmergerTag, SESSION_NOT_ALLOCATED);
580	#if defined(A18)
581	STSYS_WriteTCReg16LE((void )&SessionInfo_p->SessionEMMFilterOffset, session TC_Params_p->TC_SizeOfEMMFilter);
582	#endif
583	/* Set SlotInterrupt in the Interrupt Mask */
584	STSYS_SetTCMask16LE((void *)&SessionInfo_p->SessionInterruptMask0, STATUS_FLAGS_PACKET_SIGNAL);
585	STSYS_SetTCMask16LE((void *)&SessionInfo_p->SessionInterruptMask0, STATUS_FLAGS_PACKET_SIGNAL_RECORD_BUFFER);
586	}
587	//Init SessionInfo (stptiHelper_TCInit_SessionInfo)
588	// ******************************************
589	// ******************************************
590	//Init SlotList (stptiHelper_SlotList_Init)
591	//fixme: weggelassen, hier holen sie sich speicher fuer die Slots der Sessions; etc
592	//->PrivateData
593	//Init SlotList (stptiHelper_SlotList_Init)
594	// ******************************************
595	// ******************************************
596	//Init Interrupt DMA (stptiHelper_TCInit_InterruptDMA)
597	TCInterruptDMAConfig_p = (TCInterruptDMAConfig_t *) TC_Params_p->TC_InterruptDMAConfigStart;
598	/* Adjust the buffer size to make sure it is valid */
599	DMABufferSize = stpti_BufferSizeAdjust(sizeof(TCStatus_t) * NO_OF_STATUS_BLOCKS);
600	pti->InterruptDMABufferSize = DMABufferSize + DMAScratchAreaSize;
601	#if 0
602	base_p = (u8 *)dma_alloc_coherent(NULL,
603	pti->InterruptDMABufferSize,
604	(dma_addr_t *) & (pti->InterruptDMABufferInfo),
605	GFP_KERNEL);
606	#else
607	base_p = kmalloc(pti->InterruptDMABufferSize, GFP_KERNEL \| __GFP_DMA);
608	#endif
609	if (base_p == NULL)
610	{
611	printk("!!!!!!!!!! NO MEMORY !!!!!!!!!!!!!!!\n");
612	pti->InterruptBufferStart_p = NULL;
613	return;
614	}
615	#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,32)
616	__flush_purge_region((void *) base_p, DMABufferSize + DMAScratchAreaSize);
617	#else
618	dma_cache_wback_inv((void *) base_p, DMABufferSize + DMAScratchAreaSize);
619	#endif
620	base_p = stpti_BufferBaseAdjust(base_p);
621	pti->InterruptBufferStart_p = base_p;
622	#if defined (CONFIG_KERNELVERSION) \|\| LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,32)
623	/* Convert to a physical address for TC. */
624	base_p = (u8 *)virt_to_phys(base_p);
625	#else
626	/* Convert to a physical address for TC. */
627	base_p = (u8 *)virt_to_bus(base_p);
628	#endif
629	/* Sort out base and top alignment */
630	top_p = base_p + DMABufferSize;
631	/* set top_p, btm, read_p & write_p ( qwrite_p etc not required ) */
632	writel((u32) base_p, (void *)&TCInterruptDMAConfig_p->DMABase_p);
633	writel(((u32) top_p - 1) & ~0X0f , (void *)&TCInterruptDMAConfig_p->DMATop_p);
634	writel((u32) base_p , (void *)&TCInterruptDMAConfig_p->DMARead_p);
635	writel((u32) base_p , (void *)&TCInterruptDMAConfig_p->DMAWrite_p);
636	//Init Interrupt DMA (stptiHelper_TCInit_InterruptDMA)
637	// ******************************************
638	// ******************************************
639	//Alloc PrivateData (stptiHelper_TCInit_AllocPrivateData)
640	//fixme erstmal wechgelassen (SlotHandle etc werden alloziiert)
641	//Alloc PrivateData
642	// ******************************************
643	// ******************************************
644	//TcCam Init (TcCam_Initialize)
645	TC_SectionFilterArrays_p = (TCSectionFilterArrays_t *) &TC_Device->TC_SectionFilterArrays;
646	//ClearAllCams( TC_SectionFilterArrays_p );
647	for (block = 0; block < SF_NUM_BLOCKS_PER_CAM; block++)
648	{
649	for (index = 0; index < SF_FILTER_LENGTH; index++)
650	{
651	TC_SectionFilterArrays_p->CamA_Block[block].Index[index].Data.Word = 0xffffffff;
652	TC_SectionFilterArrays_p->CamA_Block[block].Index[index].Mask.Word = 0xffffffff;
653	TC_SectionFilterArrays_p->CamB_Block[block].Index[index].Data.Word = 0xffffffff;
654	TC_SectionFilterArrays_p->CamB_Block[block].Index[index].Mask.Word = 0xffffffff;
655	}
656	}
657	for (index = 0; index < TC_NUMBER_OF_HARDWARE_NOT_FILTERS; index++)
658	{
659	TC_SectionFilterArrays_p->NotFilter[index] = 0;
660	}
661	//fixme: auch hier hab ich die ganze interne verwaltung wegoptimiert ;-)
662	//TcCam Init (TcCam_Initialize)
663	// ******************************************
664	// ******************************************
665	//Start (stptiHelper_TCInit_Start)
666	#if 0
667	STSYS_WriteRegDev32LE((void )&TC_Device->TCMode, 0x08); / Full Reset the TC */
668	udelay(200 * 64); /* 12800us / / Wait */
669	STSYS_WriteRegDev32LE((void )&TC_Device->TCMode, 0x00); / Finish Full Reset the TC */
670	udelay(10 * 64); /* 640us */
671	#endif
672	writel(1, (void *)&TC_Device->IIFFIFOEnable);
673	writel(2, (void *)&TC_Device->TCMode);
674	writel(1, (void *)&TC_Device->TCMode);
675	}
676
677	int __init pti_init(void)
678	{
679	printk("pti loaded (videoMem = %d, waitMS = %d", videoMem, waitMS);
680	#ifdef WITH_CAMROUTING
681	printk(", camRouting = %d", camRouting);
682	#endif
683	#ifdef CONFIG_PRINTK
684	printk(", enableStatistic = %d", enableStatistic);
685	#else
686	printk(", enableSysStatistic = %d", enableSysStatistic);
687	#endif
688	printk(")\n");
689	return 0;
690	}
691
692	void __exit pti_exit(void)
693	{
694	printk("pti unloaded\n");
695	}
696
697	module_init(pti_init);
698	module_exit(pti_exit);
699
700	MODULE_DESCRIPTION("PTI driver");
701	MODULE_AUTHOR("Team Ducktales");
702	MODULE_LICENSE("NO");
703
704	#ifdef WITH_CAMROUTING
705	module_param(camRouting, int, S_IRUSR \| S_IWUSR \| S_IRGRP \| S_IWGRP);
706	MODULE_PARM_DESC(camRouting, "ufs910 only! 1=if stream not scrambled do not route it through cimax");
707	#endif
708
709	module_param(videoMem, int, S_IRUSR \| S_IWUSR \| S_IRGRP \| S_IWGRP);
710	MODULE_PARM_DESC(videoMem, "memory for video pid buffer in dvb packets (188 byte). default 2048");
711
712	module_param(waitMS, int, S_IRUSR \| S_IWUSR \| S_IRGRP \| S_IWGRP);
713	MODULE_PARM_DESC(waitMS, "waiting time in ms before processing next data (default=20)");
714
715	#ifdef CONFIG_PRINTK
716	module_param(enableStatistic, int, S_IRUSR \| S_IWUSR \| S_IRGRP \| S_IWGRP);
717	MODULE_PARM_DESC(enableStatistic, "enable statistic output on pids arriving pti (default=0=disabled)");
718	#else
719	module_param(enableSysStatistic, int, S_IRUSR \| S_IWUSR \| S_IRGRP \| S_IWGRP);
720	MODULE_PARM_DESC(enableSysStatistic, "enable sys statistic output on pids arriving pti (default=1=disabled)");
721
722	module_param(pti_last_time, ulong, S_IRUSR \| S_IRGRP);
723	MODULE_PARM_DESC(pti_last_time, "last time pti task called");
724
725	module_param(pti_count, ulong, S_IRUSR \| S_IRGRP);
726	MODULE_PARM_DESC(pti_count, "pti package counter");
727	#endif

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source: tools/oebuild/data/pti_np/pti_main.c @ 45168

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